1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Mainboard vendor" 9 default VENDOR_EMULATION 10 11config VENDOR_CONGATEC 12 bool "congatec" 13 14config VENDOR_COREBOOT 15 bool "coreboot" 16 17config VENDOR_EFI 18 bool "efi" 19 20config VENDOR_EMULATION 21 bool "emulation" 22 23config VENDOR_GOOGLE 24 bool "Google" 25 26config VENDOR_INTEL 27 bool "Intel" 28 29endchoice 30 31# board-specific options below 32source "board/congatec/Kconfig" 33source "board/coreboot/Kconfig" 34source "board/efi/Kconfig" 35source "board/emulation/Kconfig" 36source "board/google/Kconfig" 37source "board/intel/Kconfig" 38 39# platform-specific options below 40source "arch/x86/cpu/baytrail/Kconfig" 41source "arch/x86/cpu/broadwell/Kconfig" 42source "arch/x86/cpu/coreboot/Kconfig" 43source "arch/x86/cpu/ivybridge/Kconfig" 44source "arch/x86/cpu/qemu/Kconfig" 45source "arch/x86/cpu/quark/Kconfig" 46source "arch/x86/cpu/queensbay/Kconfig" 47 48# architecture-specific options below 49 50config AHCI 51 default y 52 53config SYS_MALLOC_F_LEN 54 default 0x800 55 56config RAMBASE 57 hex 58 default 0x100000 59 60config XIP_ROM_SIZE 61 hex 62 depends on X86_RESET_VECTOR 63 default ROM_SIZE 64 65config CPU_ADDR_BITS 66 int 67 default 36 68 69config HPET_ADDRESS 70 hex 71 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 72 73config SMM_TSEG 74 bool 75 default n 76 77config SMM_TSEG_SIZE 78 hex 79 80config X86_RESET_VECTOR 81 bool 82 default n 83 84config RESET_SEG_START 85 hex 86 depends on X86_RESET_VECTOR 87 default 0xffff0000 88 89config RESET_SEG_SIZE 90 hex 91 depends on X86_RESET_VECTOR 92 default 0x10000 93 94config RESET_VEC_LOC 95 hex 96 depends on X86_RESET_VECTOR 97 default 0xfffffff0 98 99config SYS_X86_START16 100 hex 101 depends on X86_RESET_VECTOR 102 default 0xfffff800 103 104config BOARD_ROMSIZE_KB_512 105 bool 106config BOARD_ROMSIZE_KB_1024 107 bool 108config BOARD_ROMSIZE_KB_2048 109 bool 110config BOARD_ROMSIZE_KB_4096 111 bool 112config BOARD_ROMSIZE_KB_8192 113 bool 114config BOARD_ROMSIZE_KB_16384 115 bool 116 117choice 118 prompt "ROM chip size" 119 depends on X86_RESET_VECTOR 120 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 121 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 122 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 123 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 124 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 125 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 126 help 127 Select the size of the ROM chip you intend to flash U-Boot on. 128 129 The build system will take care of creating a u-boot.rom file 130 of the matching size. 131 132config UBOOT_ROMSIZE_KB_512 133 bool "512 KB" 134 help 135 Choose this option if you have a 512 KB ROM chip. 136 137config UBOOT_ROMSIZE_KB_1024 138 bool "1024 KB (1 MB)" 139 help 140 Choose this option if you have a 1024 KB (1 MB) ROM chip. 141 142config UBOOT_ROMSIZE_KB_2048 143 bool "2048 KB (2 MB)" 144 help 145 Choose this option if you have a 2048 KB (2 MB) ROM chip. 146 147config UBOOT_ROMSIZE_KB_4096 148 bool "4096 KB (4 MB)" 149 help 150 Choose this option if you have a 4096 KB (4 MB) ROM chip. 151 152config UBOOT_ROMSIZE_KB_8192 153 bool "8192 KB (8 MB)" 154 help 155 Choose this option if you have a 8192 KB (8 MB) ROM chip. 156 157config UBOOT_ROMSIZE_KB_16384 158 bool "16384 KB (16 MB)" 159 help 160 Choose this option if you have a 16384 KB (16 MB) ROM chip. 161 162endchoice 163 164# Map the config names to an integer (KB). 165config UBOOT_ROMSIZE_KB 166 int 167 default 512 if UBOOT_ROMSIZE_KB_512 168 default 1024 if UBOOT_ROMSIZE_KB_1024 169 default 2048 if UBOOT_ROMSIZE_KB_2048 170 default 4096 if UBOOT_ROMSIZE_KB_4096 171 default 8192 if UBOOT_ROMSIZE_KB_8192 172 default 16384 if UBOOT_ROMSIZE_KB_16384 173 174# Map the config names to a hex value (bytes). 175config ROM_SIZE 176 hex 177 default 0x80000 if UBOOT_ROMSIZE_KB_512 178 default 0x100000 if UBOOT_ROMSIZE_KB_1024 179 default 0x200000 if UBOOT_ROMSIZE_KB_2048 180 default 0x400000 if UBOOT_ROMSIZE_KB_4096 181 default 0x800000 if UBOOT_ROMSIZE_KB_8192 182 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 183 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 184 185config HAVE_INTEL_ME 186 bool "Platform requires Intel Management Engine" 187 help 188 Newer higher-end devices have an Intel Management Engine (ME) 189 which is a very large binary blob (typically 1.5MB) which is 190 required for the platform to work. This enforces a particular 191 SPI flash format. You will need to supply the me.bin file in 192 your board directory. 193 194config X86_RAMTEST 195 bool "Perform a simple RAM test after SDRAM initialisation" 196 help 197 If there is something wrong with SDRAM then the platform will 198 often crash within U-Boot or the kernel. This option enables a 199 very simple RAM test that quickly checks whether the SDRAM seems 200 to work correctly. It is not exhaustive but can save time by 201 detecting obvious failures. 202 203config HAVE_FSP 204 bool "Add an Firmware Support Package binary" 205 depends on !EFI 206 help 207 Select this option to add an Firmware Support Package binary to 208 the resulting U-Boot image. It is a binary blob which U-Boot uses 209 to set up SDRAM and other chipset specific initialization. 210 211 Note: Without this binary U-Boot will not be able to set up its 212 SDRAM so will not boot. 213 214config FSP_FILE 215 string "Firmware Support Package binary filename" 216 depends on HAVE_FSP 217 default "fsp.bin" 218 help 219 The filename of the file to use as Firmware Support Package binary 220 in the board directory. 221 222config FSP_ADDR 223 hex "Firmware Support Package binary location" 224 depends on HAVE_FSP 225 default 0xfffc0000 226 help 227 FSP is not Position Independent Code (PIC) and the whole FSP has to 228 be rebased if it is placed at a location which is different from the 229 perferred base address specified during the FSP build. Use Intel's 230 Binary Configuration Tool (BCT) to do the rebase. 231 232 The default base address of 0xfffc0000 indicates that the binary must 233 be located at offset 0xc0000 from the beginning of a 1MB flash device. 234 235config FSP_TEMP_RAM_ADDR 236 hex 237 depends on HAVE_FSP 238 default 0x2000000 239 help 240 Stack top address which is used in fsp_init() after DRAM is ready and 241 CAR is disabled. 242 243config FSP_SYS_MALLOC_F_LEN 244 hex 245 depends on HAVE_FSP 246 default 0x100000 247 help 248 Additional size of malloc() pool before relocation. 249 250config FSP_USE_UPD 251 bool 252 depends on HAVE_FSP 253 default y 254 help 255 Most FSPs use UPD data region for some FSP customization. But there 256 are still some FSPs that might not even have UPD. For such FSPs, 257 override this to n in their platform Kconfig files. 258 259config FSP_BROKEN_HOB 260 bool 261 depends on HAVE_FSP 262 help 263 Indicate some buggy FSPs that does not report memory used by FSP 264 itself as reserved in the resource descriptor HOB. Select this to 265 tell U-Boot to do some additional work to ensure U-Boot relocation 266 do not overwrite the important boot service data which is used by 267 FSP, otherwise the subsequent call to fsp_notify() will fail. 268 269config ENABLE_MRC_CACHE 270 bool "Enable MRC cache" 271 depends on !EFI && !SYS_COREBOOT 272 help 273 Enable this feature to cause MRC data to be cached in NV storage 274 to be used for speeding up boot time on future reboots and/or 275 power cycles. 276 277 For platforms that use Intel FSP for the memory initialization, 278 please check FSP output HOB via U-Boot command 'fsp hob' to see 279 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 280 If such GUID does not exist, MRC cache is not avaiable on such 281 platform (eg: Intel Queensbay), which means selecting this option 282 here does not make any difference. 283 284config HAVE_MRC 285 bool "Add a System Agent binary" 286 depends on !HAVE_FSP 287 help 288 Select this option to add a System Agent binary to 289 the resulting U-Boot image. MRC stands for Memory Reference Code. 290 It is a binary blob which U-Boot uses to set up SDRAM. 291 292 Note: Without this binary U-Boot will not be able to set up its 293 SDRAM so will not boot. 294 295config CACHE_MRC_BIN 296 bool 297 depends on HAVE_MRC 298 default n 299 help 300 Enable caching for the memory reference code binary. This uses an 301 MTRR (memory type range register) to turn on caching for the section 302 of SPI flash that contains the memory reference code. This makes 303 SDRAM init run faster. 304 305config CACHE_MRC_SIZE_KB 306 int 307 depends on HAVE_MRC 308 default 512 309 help 310 Sets the size of the cached area for the memory reference code. 311 This ends at the end of SPI flash (address 0xffffffff) and is 312 measured in KB. Typically this is set to 512, providing for 0.5MB 313 of cached space. 314 315config DCACHE_RAM_BASE 316 hex 317 depends on HAVE_MRC 318 help 319 Sets the base of the data cache area in memory space. This is the 320 start address of the cache-as-RAM (CAR) area and the address varies 321 depending on the CPU. Once CAR is set up, read/write memory becomes 322 available at this address and can be used temporarily until SDRAM 323 is working. 324 325config DCACHE_RAM_SIZE 326 hex 327 depends on HAVE_MRC 328 default 0x40000 329 help 330 Sets the total size of the data cache area in memory space. This 331 sets the size of the cache-as-RAM (CAR) area. Note that much of the 332 CAR space is required by the MRC. The CAR space available to U-Boot 333 is normally at the start and typically extends to 1/4 or 1/2 of the 334 available size. 335 336config DCACHE_RAM_MRC_VAR_SIZE 337 hex 338 depends on HAVE_MRC 339 help 340 This is the amount of CAR (Cache as RAM) reserved for use by the 341 memory reference code. This depends on the implementation of the 342 memory reference code and must be set correctly or the board will 343 not boot. 344 345config HAVE_REFCODE 346 bool "Add a Reference Code binary" 347 help 348 Select this option to add a Reference Code binary to the resulting 349 U-Boot image. This is an Intel binary blob that handles system 350 initialisation, in this case the PCH and System Agent. 351 352 Note: Without this binary (on platforms that need it such as 353 broadwell) U-Boot will be missing some critical setup steps. 354 Various peripherals may fail to work. 355 356config SMP 357 bool "Enable Symmetric Multiprocessing" 358 default n 359 help 360 Enable use of more than one CPU in U-Boot and the Operating System 361 when loaded. Each CPU will be started up and information can be 362 obtained using the 'cpu' command. If this option is disabled, then 363 only one CPU will be enabled regardless of the number of CPUs 364 available. 365 366config MAX_CPUS 367 int "Maximum number of CPUs permitted" 368 depends on SMP 369 default 4 370 help 371 When using multi-CPU chips it is possible for U-Boot to start up 372 more than one CPU. The stack memory used by all of these CPUs is 373 pre-allocated so at present U-Boot wants to know the maximum 374 number of CPUs that may be present. Set this to at least as high 375 as the number of CPUs in your system (it uses about 4KB of RAM for 376 each CPU). 377 378config AP_STACK_SIZE 379 hex 380 depends on SMP 381 default 0x1000 382 help 383 Each additional CPU started by U-Boot requires its own stack. This 384 option sets the stack size used by each CPU and directly affects 385 the memory used by this initialisation process. Typically 4KB is 386 enough space. 387 388config HAVE_VGA_BIOS 389 bool "Add a VGA BIOS image" 390 help 391 Select this option if you have a VGA BIOS image that you would 392 like to add to your ROM. 393 394config VGA_BIOS_FILE 395 string "VGA BIOS image filename" 396 depends on HAVE_VGA_BIOS 397 default "vga.bin" 398 help 399 The filename of the VGA BIOS image in the board directory. 400 401config VGA_BIOS_ADDR 402 hex "VGA BIOS image location" 403 depends on HAVE_VGA_BIOS 404 default 0xfff90000 405 help 406 The location of VGA BIOS image in the SPI flash. For example, base 407 address of 0xfff90000 indicates that the image will be put at offset 408 0x90000 from the beginning of a 1MB flash device. 409 410menu "System tables" 411 depends on !EFI && !SYS_COREBOOT 412 413config GENERATE_PIRQ_TABLE 414 bool "Generate a PIRQ table" 415 default n 416 help 417 Generate a PIRQ routing table for this board. The PIRQ routing table 418 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 419 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 420 It specifies the interrupt router information as well how all the PCI 421 devices' interrupt pins are wired to PIRQs. 422 423config GENERATE_SFI_TABLE 424 bool "Generate a SFI (Simple Firmware Interface) table" 425 help 426 The Simple Firmware Interface (SFI) provides a lightweight method 427 for platform firmware to pass information to the operating system 428 via static tables in memory. Kernel SFI support is required to 429 boot on SFI-only platforms. If you have ACPI tables then these are 430 used instead. 431 432 U-Boot writes this table in write_sfi_table() just before booting 433 the OS. 434 435 For more information, see http://simplefirmware.org 436 437config GENERATE_MP_TABLE 438 bool "Generate an MP (Multi-Processor) table" 439 default n 440 help 441 Generate an MP (Multi-Processor) table for this board. The MP table 442 provides a way for the operating system to support for symmetric 443 multiprocessing as well as symmetric I/O interrupt handling with 444 the local APIC and I/O APIC. 445 446config GENERATE_ACPI_TABLE 447 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 448 default n 449 select QFW if QEMU 450 help 451 The Advanced Configuration and Power Interface (ACPI) specification 452 provides an open standard for device configuration and management 453 by the operating system. It defines platform-independent interfaces 454 for configuration and power management monitoring. 455 456config GENERATE_SMBIOS_TABLE 457 bool "Generate an SMBIOS (System Management BIOS) table" 458 default y 459 help 460 The System Management BIOS (SMBIOS) specification addresses how 461 motherboard and system vendors present management information about 462 their products in a standard format by extending the BIOS interface 463 on Intel architecture systems. 464 465 Check http://www.dmtf.org/standards/smbios for details. 466 467config SMBIOS_MANUFACTURER 468 string "SMBIOS Manufacturer" 469 depends on GENERATE_SMBIOS_TABLE 470 default SYS_VENDOR 471 help 472 The board manufacturer to store in SMBIOS structures. 473 Change this to override the default one (CONFIG_SYS_VENDOR). 474 475config SMBIOS_PRODUCT_NAME 476 string "SMBIOS Product Name" 477 depends on GENERATE_SMBIOS_TABLE 478 default SYS_BOARD 479 help 480 The product name to store in SMBIOS structures. 481 Change this to override the default one (CONFIG_SYS_BOARD). 482 483endmenu 484 485config MAX_PIRQ_LINKS 486 int 487 default 8 488 help 489 This variable specifies the number of PIRQ interrupt links which are 490 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 491 Some newer chipsets offer more than four links, commonly up to PIRQH. 492 493config IRQ_SLOT_COUNT 494 int 495 default 128 496 help 497 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 498 which in turns forms a table of exact 4KiB. The default value 128 499 should be enough for most boards. If this does not fit your board, 500 change it according to your needs. 501 502config PCIE_ECAM_BASE 503 hex 504 default 0xe0000000 505 help 506 This is the memory-mapped address of PCI configuration space, which 507 is only available through the Enhanced Configuration Access 508 Mechanism (ECAM) with PCI Express. It can be set up almost 509 anywhere. Before it is set up, it is possible to access PCI 510 configuration space through I/O access, but memory access is more 511 convenient. Using this, PCI can be scanned and configured. This 512 should be set to a region that does not conflict with memory 513 assigned to PCI devices - i.e. the memory and prefetch regions, as 514 passed to pci_set_region(). 515 516config PCIE_ECAM_SIZE 517 hex 518 default 0x10000000 519 help 520 This is the size of memory-mapped address of PCI configuration space, 521 which is only available through the Enhanced Configuration Access 522 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 523 so a default 0x10000000 size covers all of the 256 buses which is the 524 maximum number of PCI buses as defined by the PCI specification. 525 526config I8259_PIC 527 bool 528 default y 529 help 530 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 531 slave) interrupt controllers. Include this to have U-Boot set up 532 the interrupt correctly. 533 534config I8254_TIMER 535 bool 536 default y 537 help 538 Intel 8254 timer contains three counters which have fixed uses. 539 Include this to have U-Boot set up the timer correctly. 540 541config I8042_KEYB 542 default y 543 544config DM_KEYBOARD 545 default y 546 547config SEABIOS 548 bool "Support booting SeaBIOS" 549 help 550 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 551 It can run in an emulator or natively on X86 hardware with the use 552 of coreboot/U-Boot. By turning on this option, U-Boot prepares 553 all the configuration tables that are necessary to boot SeaBIOS. 554 555 Check http://www.seabios.org/SeaBIOS for details. 556 557config HIGH_TABLE_SIZE 558 hex "Size of configuration tables which reside in high memory" 559 default 0x10000 560 depends on SEABIOS 561 help 562 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 563 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 564 puts a copy of configuration tables in high memory region which 565 is reserved on the stack before relocation. The region size is 566 determined by this option. 567 568 Increse it if the default size does not fit the board's needs. 569 This is most likely due to a large ACPI DSDT table is used. 570 571source "arch/x86/lib/efi/Kconfig" 572 573endmenu 574