1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7config USE_PRIVATE_LIBGCC 8 default y 9 10choice 11 prompt "Target select" 12 13config TARGET_COREBOOT 14 bool "Support coreboot" 15 help 16 This target is used for running U-Boot on top of Coreboot. In 17 this case Coreboot does the early inititalisation, and U-Boot 18 takes over once the RAM, video and CPU are fully running. 19 U-Boot is loaded as a fallback payload from Coreboot, in 20 Coreboot terminology. This method was used for the Chromebook 21 Pixel when launched. 22 23config TARGET_CHROMEBOOK_LINK 24 bool "Support Chromebook link" 25 help 26 This is the Chromebook Pixel released in 2013. It uses an Intel 27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of 28 SDRAM. It has a Panther Point platform controller hub, PCIe 29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD 30 reader, microphone and speakers, display port and 32GB SATA 31 solid state drive. There is a Chrome OS EC connected on LPC, 32 and it provides a 2560x1700 high resolution touch-enabled LCD 33 display. 34 35config TARGET_CHROMEBOX_PANTHER 36 bool "Support Chromebox panther (not available)" 37 select n 38 help 39 Note: At present this must be used with Coreboot. See README.x86 40 for instructions. 41 42 This is the Asus Chromebox CN60 released in 2014. It uses an Intel 43 Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a 44 Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also 45 includes a USB SD reader, four USB3 ports, display port and HDMI 46 video output and a 16GB SATA solid state drive. There is no Chrome 47 OS EC on this model. 48 49config TARGET_CROWNBAY 50 bool "Support Intel Crown Bay CRB" 51 help 52 This is the Intel Crown Bay Customer Reference Board. It contains 53 the Intel Atom Processor E6xx populated on the COM Express module 54 with 1GB DDR2 soldered down memory and a carrier board with the 55 Intel Platform Controller Hub EG20T, other system components and 56 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. 57 58config TARGET_MINNOWMAX 59 bool "Support Intel Minnowboard MAX" 60 help 61 This is the Intel Minnowboard MAX. It contains an Atom E3800 62 processor in a small form factor with Ethernet, micro-SD, USB 2, 63 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. 64 It requires some binary blobs - see README.x86 for details. 65 66 Note that PCIE_ECAM_BASE is set up by the FSP so the value used 67 by U-Boot matches that value. 68 69config TARGET_GALILEO 70 bool "Support Intel Galileo" 71 help 72 This is the Intel Galileo board, which is the first in a family of 73 Arduino-certified development and prototyping boards based on Intel 74 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit 75 single-core, single-thread, Intel Pentium processor instrunction set 76 architecture (ISA) compatible, operating at speeds up to 400Mhz, 77 along with 256MB DDR3 memory. It supports a wide range of industry 78 standard I/O interfaces, including a full-sized mini-PCIe slot, 79 one 100Mb Ethernet port, a microSD card slot, a USB host port and 80 a USB client port. 81 82endchoice 83 84config DM_SPI 85 default y 86 87config DM_SPI_FLASH 88 default y 89 90config SYS_MALLOC_F_LEN 91 default 0x800 92 93config RAMBASE 94 hex 95 default 0x100000 96 97config XIP_ROM_SIZE 98 hex 99 depends on X86_RESET_VECTOR 100 default ROM_SIZE 101 102config CPU_ADDR_BITS 103 int 104 default 36 105 106config HPET_ADDRESS 107 hex 108 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 109 110config SMM_TSEG 111 bool 112 default n 113 114config SMM_TSEG_SIZE 115 hex 116 117config X86_RESET_VECTOR 118 bool 119 default n 120 121config SYS_X86_START16 122 hex 123 depends on X86_RESET_VECTOR 124 default 0xfffff800 125 126config BOARD_ROMSIZE_KB_512 127 bool 128config BOARD_ROMSIZE_KB_1024 129 bool 130config BOARD_ROMSIZE_KB_2048 131 bool 132config BOARD_ROMSIZE_KB_4096 133 bool 134config BOARD_ROMSIZE_KB_8192 135 bool 136config BOARD_ROMSIZE_KB_16384 137 bool 138 139choice 140 prompt "ROM chip size" 141 depends on X86_RESET_VECTOR 142 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 143 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 144 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 145 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 146 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 147 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 148 help 149 Select the size of the ROM chip you intend to flash U-Boot on. 150 151 The build system will take care of creating a u-boot.rom file 152 of the matching size. 153 154config UBOOT_ROMSIZE_KB_512 155 bool "512 KB" 156 help 157 Choose this option if you have a 512 KB ROM chip. 158 159config UBOOT_ROMSIZE_KB_1024 160 bool "1024 KB (1 MB)" 161 help 162 Choose this option if you have a 1024 KB (1 MB) ROM chip. 163 164config UBOOT_ROMSIZE_KB_2048 165 bool "2048 KB (2 MB)" 166 help 167 Choose this option if you have a 2048 KB (2 MB) ROM chip. 168 169config UBOOT_ROMSIZE_KB_4096 170 bool "4096 KB (4 MB)" 171 help 172 Choose this option if you have a 4096 KB (4 MB) ROM chip. 173 174config UBOOT_ROMSIZE_KB_8192 175 bool "8192 KB (8 MB)" 176 help 177 Choose this option if you have a 8192 KB (8 MB) ROM chip. 178 179config UBOOT_ROMSIZE_KB_16384 180 bool "16384 KB (16 MB)" 181 help 182 Choose this option if you have a 16384 KB (16 MB) ROM chip. 183 184endchoice 185 186# Map the config names to an integer (KB). 187config UBOOT_ROMSIZE_KB 188 int 189 default 512 if UBOOT_ROMSIZE_KB_512 190 default 1024 if UBOOT_ROMSIZE_KB_1024 191 default 2048 if UBOOT_ROMSIZE_KB_2048 192 default 4096 if UBOOT_ROMSIZE_KB_4096 193 default 8192 if UBOOT_ROMSIZE_KB_8192 194 default 16384 if UBOOT_ROMSIZE_KB_16384 195 196# Map the config names to a hex value (bytes). 197config ROM_SIZE 198 hex 199 default 0x80000 if UBOOT_ROMSIZE_KB_512 200 default 0x100000 if UBOOT_ROMSIZE_KB_1024 201 default 0x200000 if UBOOT_ROMSIZE_KB_2048 202 default 0x400000 if UBOOT_ROMSIZE_KB_4096 203 default 0x800000 if UBOOT_ROMSIZE_KB_8192 204 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 205 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 206 207config HAVE_INTEL_ME 208 bool "Platform requires Intel Management Engine" 209 help 210 Newer higher-end devices have an Intel Management Engine (ME) 211 which is a very large binary blob (typically 1.5MB) which is 212 required for the platform to work. This enforces a particular 213 SPI flash format. You will need to supply the me.bin file in 214 your board directory. 215 216config X86_RAMTEST 217 bool "Perform a simple RAM test after SDRAM initialisation" 218 help 219 If there is something wrong with SDRAM then the platform will 220 often crash within U-Boot or the kernel. This option enables a 221 very simple RAM test that quickly checks whether the SDRAM seems 222 to work correctly. It is not exhaustive but can save time by 223 detecting obvious failures. 224 225config MARK_GRAPHICS_MEM_WRCOMB 226 bool "Mark graphics memory as write-combining." 227 default n 228 help 229 The graphics performance may increase if the graphics 230 memory is set as write-combining cache type. This option 231 enables marking the graphics memory as write-combining. 232 233menu "Display" 234 235config FRAMEBUFFER_SET_VESA_MODE 236 prompt "Set framebuffer graphics resolution" 237 bool 238 help 239 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) 240 241choice 242 prompt "framebuffer graphics resolution" 243 default FRAMEBUFFER_VESA_MODE_117 244 depends on FRAMEBUFFER_SET_VESA_MODE 245 help 246 This option sets the resolution used for the coreboot framebuffer (and 247 bootsplash screen). 248 249config FRAMEBUFFER_VESA_MODE_100 250 bool "640x400 256-color" 251 252config FRAMEBUFFER_VESA_MODE_101 253 bool "640x480 256-color" 254 255config FRAMEBUFFER_VESA_MODE_102 256 bool "800x600 16-color" 257 258config FRAMEBUFFER_VESA_MODE_103 259 bool "800x600 256-color" 260 261config FRAMEBUFFER_VESA_MODE_104 262 bool "1024x768 16-color" 263 264config FRAMEBUFFER_VESA_MODE_105 265 bool "1024x7686 256-color" 266 267config FRAMEBUFFER_VESA_MODE_106 268 bool "1280x1024 16-color" 269 270config FRAMEBUFFER_VESA_MODE_107 271 bool "1280x1024 256-color" 272 273config FRAMEBUFFER_VESA_MODE_108 274 bool "80x60 text" 275 276config FRAMEBUFFER_VESA_MODE_109 277 bool "132x25 text" 278 279config FRAMEBUFFER_VESA_MODE_10A 280 bool "132x43 text" 281 282config FRAMEBUFFER_VESA_MODE_10B 283 bool "132x50 text" 284 285config FRAMEBUFFER_VESA_MODE_10C 286 bool "132x60 text" 287 288config FRAMEBUFFER_VESA_MODE_10D 289 bool "320x200 32k-color (1:5:5:5)" 290 291config FRAMEBUFFER_VESA_MODE_10E 292 bool "320x200 64k-color (5:6:5)" 293 294config FRAMEBUFFER_VESA_MODE_10F 295 bool "320x200 16.8M-color (8:8:8)" 296 297config FRAMEBUFFER_VESA_MODE_110 298 bool "640x480 32k-color (1:5:5:5)" 299 300config FRAMEBUFFER_VESA_MODE_111 301 bool "640x480 64k-color (5:6:5)" 302 303config FRAMEBUFFER_VESA_MODE_112 304 bool "640x480 16.8M-color (8:8:8)" 305 306config FRAMEBUFFER_VESA_MODE_113 307 bool "800x600 32k-color (1:5:5:5)" 308 309config FRAMEBUFFER_VESA_MODE_114 310 bool "800x600 64k-color (5:6:5)" 311 312config FRAMEBUFFER_VESA_MODE_115 313 bool "800x600 16.8M-color (8:8:8)" 314 315config FRAMEBUFFER_VESA_MODE_116 316 bool "1024x768 32k-color (1:5:5:5)" 317 318config FRAMEBUFFER_VESA_MODE_117 319 bool "1024x768 64k-color (5:6:5)" 320 321config FRAMEBUFFER_VESA_MODE_118 322 bool "1024x768 16.8M-color (8:8:8)" 323 324config FRAMEBUFFER_VESA_MODE_119 325 bool "1280x1024 32k-color (1:5:5:5)" 326 327config FRAMEBUFFER_VESA_MODE_11A 328 bool "1280x1024 64k-color (5:6:5)" 329 330config FRAMEBUFFER_VESA_MODE_11B 331 bool "1280x1024 16.8M-color (8:8:8)" 332 333config FRAMEBUFFER_VESA_MODE_USER 334 bool "Manually select VESA mode" 335 336endchoice 337 338# Map the config names to an integer (KB). 339config FRAMEBUFFER_VESA_MODE 340 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER 341 hex 342 default 0x100 if FRAMEBUFFER_VESA_MODE_100 343 default 0x101 if FRAMEBUFFER_VESA_MODE_101 344 default 0x102 if FRAMEBUFFER_VESA_MODE_102 345 default 0x103 if FRAMEBUFFER_VESA_MODE_103 346 default 0x104 if FRAMEBUFFER_VESA_MODE_104 347 default 0x105 if FRAMEBUFFER_VESA_MODE_105 348 default 0x106 if FRAMEBUFFER_VESA_MODE_106 349 default 0x107 if FRAMEBUFFER_VESA_MODE_107 350 default 0x108 if FRAMEBUFFER_VESA_MODE_108 351 default 0x109 if FRAMEBUFFER_VESA_MODE_109 352 default 0x10A if FRAMEBUFFER_VESA_MODE_10A 353 default 0x10B if FRAMEBUFFER_VESA_MODE_10B 354 default 0x10C if FRAMEBUFFER_VESA_MODE_10C 355 default 0x10D if FRAMEBUFFER_VESA_MODE_10D 356 default 0x10E if FRAMEBUFFER_VESA_MODE_10E 357 default 0x10F if FRAMEBUFFER_VESA_MODE_10F 358 default 0x110 if FRAMEBUFFER_VESA_MODE_110 359 default 0x111 if FRAMEBUFFER_VESA_MODE_111 360 default 0x112 if FRAMEBUFFER_VESA_MODE_112 361 default 0x113 if FRAMEBUFFER_VESA_MODE_113 362 default 0x114 if FRAMEBUFFER_VESA_MODE_114 363 default 0x115 if FRAMEBUFFER_VESA_MODE_115 364 default 0x116 if FRAMEBUFFER_VESA_MODE_116 365 default 0x117 if FRAMEBUFFER_VESA_MODE_117 366 default 0x118 if FRAMEBUFFER_VESA_MODE_118 367 default 0x119 if FRAMEBUFFER_VESA_MODE_119 368 default 0x11A if FRAMEBUFFER_VESA_MODE_11A 369 default 0x11B if FRAMEBUFFER_VESA_MODE_11B 370 default 0x117 if FRAMEBUFFER_VESA_MODE_USER 371 372endmenu 373 374config HAVE_FSP 375 bool "Add an Firmware Support Package binary" 376 help 377 Select this option to add an Firmware Support Package binary to 378 the resulting U-Boot image. It is a binary blob which U-Boot uses 379 to set up SDRAM and other chipset specific initialization. 380 381 Note: Without this binary U-Boot will not be able to set up its 382 SDRAM so will not boot. 383 384config FSP_FILE 385 string "Firmware Support Package binary filename" 386 depends on HAVE_FSP 387 default "fsp.bin" 388 help 389 The filename of the file to use as Firmware Support Package binary 390 in the board directory. 391 392config FSP_ADDR 393 hex "Firmware Support Package binary location" 394 depends on HAVE_FSP 395 default 0xfffc0000 396 help 397 FSP is not Position Independent Code (PIC) and the whole FSP has to 398 be rebased if it is placed at a location which is different from the 399 perferred base address specified during the FSP build. Use Intel's 400 Binary Configuration Tool (BCT) to do the rebase. 401 402 The default base address of 0xfffc0000 indicates that the binary must 403 be located at offset 0xc0000 from the beginning of a 1MB flash device. 404 405config FSP_TEMP_RAM_ADDR 406 hex 407 default 0x2000000 408 help 409 Stack top address which is used in FspInit after DRAM is ready and 410 CAR is disabled. 411 412source "arch/x86/cpu/baytrail/Kconfig" 413 414source "arch/x86/cpu/coreboot/Kconfig" 415 416source "arch/x86/cpu/ivybridge/Kconfig" 417 418source "arch/x86/cpu/quark/Kconfig" 419 420source "arch/x86/cpu/queensbay/Kconfig" 421 422config TSC_CALIBRATION_BYPASS 423 bool "Bypass Time-Stamp Counter (TSC) calibration" 424 default n 425 help 426 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 427 running frequency via Model-Specific Register (MSR) and Programmable 428 Interval Timer (PIT). If the calibration does not work on your board, 429 select this option and provide a hardcoded TSC running frequency with 430 CONFIG_TSC_FREQ_IN_MHZ below. 431 432 Normally this option should be turned on in a simulation environment 433 like qemu. 434 435config TSC_FREQ_IN_MHZ 436 int "Time-Stamp Counter (TSC) running frequency in MHz" 437 depends on TSC_CALIBRATION_BYPASS 438 default 1000 439 help 440 The running frequency in MHz of Time-Stamp Counter (TSC). 441 442source "board/coreboot/coreboot/Kconfig" 443 444source "board/google/chromebook_link/Kconfig" 445 446source "board/google/chromebox_panther/Kconfig" 447 448source "board/intel/crownbay/Kconfig" 449 450source "board/intel/minnowmax/Kconfig" 451 452source "board/intel/galileo/Kconfig" 453 454config PCIE_ECAM_BASE 455 hex 456 default 0xe0000000 457 help 458 This is the memory-mapped address of PCI configuration space, which 459 is only available through the Enhanced Configuration Access 460 Mechanism (ECAM) with PCI Express. It can be set up almost 461 anywhere. Before it is set up, it is possible to access PCI 462 configuration space through I/O access, but memory access is more 463 convenient. Using this, PCI can be scanned and configured. This 464 should be set to a region that does not conflict with memory 465 assigned to PCI devices - i.e. the memory and prefetch regions, as 466 passed to pci_set_region(). 467 468endmenu 469