1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SUPPORT_SPL 36 select SPL 37 select SPL_SEPARATE_BSS 38 help 39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 40 experimental and many features are missing. U-Boot SPL starts up, 41 runs through the 16-bit and 32-bit init, then switches to 64-bit 42 mode and jumps to U-Boot proper. 43 44endchoice 45 46config X86_64 47 bool 48 49config SPL_X86_64 50 bool 51 depends on SPL 52 53choice 54 prompt "Mainboard vendor" 55 default VENDOR_EMULATION 56 57config VENDOR_ADVANTECH 58 bool "advantech" 59 60config VENDOR_CONGATEC 61 bool "congatec" 62 63config VENDOR_COREBOOT 64 bool "coreboot" 65 66config VENDOR_DFI 67 bool "dfi" 68 69config VENDOR_EFI 70 bool "efi" 71 72config VENDOR_EMULATION 73 bool "emulation" 74 75config VENDOR_GOOGLE 76 bool "Google" 77 78config VENDOR_INTEL 79 bool "Intel" 80 81endchoice 82 83# subarchitectures-specific options below 84config INTEL_MID 85 bool "Intel MID platform support" 86 select REGMAP 87 select SYSCON 88 help 89 Select to build a U-Boot capable of supporting Intel MID 90 (Mobile Internet Device) platform systems which do not have 91 the PCI legacy interfaces. 92 93 If you are building for a PC class system say N here. 94 95 Intel MID platforms are based on an Intel processor and 96 chipset which consume less power than most of the x86 97 derivatives. 98 99# board-specific options below 100source "board/advantech/Kconfig" 101source "board/congatec/Kconfig" 102source "board/coreboot/Kconfig" 103source "board/dfi/Kconfig" 104source "board/efi/Kconfig" 105source "board/emulation/Kconfig" 106source "board/google/Kconfig" 107source "board/intel/Kconfig" 108 109# platform-specific options below 110source "arch/x86/cpu/baytrail/Kconfig" 111source "arch/x86/cpu/broadwell/Kconfig" 112source "arch/x86/cpu/coreboot/Kconfig" 113source "arch/x86/cpu/ivybridge/Kconfig" 114source "arch/x86/cpu/qemu/Kconfig" 115source "arch/x86/cpu/quark/Kconfig" 116source "arch/x86/cpu/queensbay/Kconfig" 117source "arch/x86/cpu/tangier/Kconfig" 118 119# architecture-specific options below 120 121config AHCI 122 default y 123 124config SYS_MALLOC_F_LEN 125 default 0x800 126 127config RAMBASE 128 hex 129 default 0x100000 130 131config XIP_ROM_SIZE 132 hex 133 depends on X86_RESET_VECTOR 134 default ROM_SIZE 135 136config CPU_ADDR_BITS 137 int 138 default 36 139 140config HPET_ADDRESS 141 hex 142 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 143 144config SMM_TSEG 145 bool 146 default n 147 148config SMM_TSEG_SIZE 149 hex 150 151config X86_RESET_VECTOR 152 bool 153 default n 154 155# The following options control where the 16-bit and 32-bit init lies 156# If SPL is enabled then it normally holds this init code, and U-Boot proper 157# is normally a 64-bit build. 158# 159# The 16-bit init refers to the reset vector and the small amount of code to 160# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 161# or missing altogether if U-Boot is started from EFI or coreboot. 162# 163# The 32-bit init refers to processor init, running binary blobs including 164# FSP, setting up interrupts and anything else that needs to be done in 165# 32-bit code. It is normally in the same place as 16-bit init if that is 166# enabled (i.e. they are both in SPL, or both in U-Boot proper). 167config X86_16BIT_INIT 168 bool 169 depends on X86_RESET_VECTOR 170 default y if X86_RESET_VECTOR && !SPL 171 help 172 This is enabled when 16-bit init is in U-Boot proper 173 174config SPL_X86_16BIT_INIT 175 bool 176 depends on X86_RESET_VECTOR 177 default y if X86_RESET_VECTOR && SPL 178 help 179 This is enabled when 16-bit init is in SPL 180 181config X86_32BIT_INIT 182 bool 183 depends on X86_RESET_VECTOR 184 default y if X86_RESET_VECTOR && !SPL 185 help 186 This is enabled when 32-bit init is in U-Boot proper 187 188config SPL_X86_32BIT_INIT 189 bool 190 depends on X86_RESET_VECTOR 191 default y if X86_RESET_VECTOR && SPL 192 help 193 This is enabled when 32-bit init is in SPL 194 195config RESET_SEG_START 196 hex 197 depends on X86_RESET_VECTOR 198 default 0xffff0000 199 200config RESET_SEG_SIZE 201 hex 202 depends on X86_RESET_VECTOR 203 default 0x10000 204 205config RESET_VEC_LOC 206 hex 207 depends on X86_RESET_VECTOR 208 default 0xfffffff0 209 210config SYS_X86_START16 211 hex 212 depends on X86_RESET_VECTOR 213 default 0xfffff800 214 215config X86_LOAD_FROM_32_BIT 216 bool "Boot from a 32-bit program" 217 help 218 Define this to boot U-Boot from a 32-bit program which sets 219 the GDT differently. This can be used to boot directly from 220 any stage of coreboot, for example, bypassing the normal 221 payload-loading feature. 222 223config BOARD_ROMSIZE_KB_512 224 bool 225config BOARD_ROMSIZE_KB_1024 226 bool 227config BOARD_ROMSIZE_KB_2048 228 bool 229config BOARD_ROMSIZE_KB_4096 230 bool 231config BOARD_ROMSIZE_KB_8192 232 bool 233config BOARD_ROMSIZE_KB_16384 234 bool 235 236choice 237 prompt "ROM chip size" 238 depends on X86_RESET_VECTOR 239 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 240 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 241 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 242 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 243 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 244 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 245 help 246 Select the size of the ROM chip you intend to flash U-Boot on. 247 248 The build system will take care of creating a u-boot.rom file 249 of the matching size. 250 251config UBOOT_ROMSIZE_KB_512 252 bool "512 KB" 253 help 254 Choose this option if you have a 512 KB ROM chip. 255 256config UBOOT_ROMSIZE_KB_1024 257 bool "1024 KB (1 MB)" 258 help 259 Choose this option if you have a 1024 KB (1 MB) ROM chip. 260 261config UBOOT_ROMSIZE_KB_2048 262 bool "2048 KB (2 MB)" 263 help 264 Choose this option if you have a 2048 KB (2 MB) ROM chip. 265 266config UBOOT_ROMSIZE_KB_4096 267 bool "4096 KB (4 MB)" 268 help 269 Choose this option if you have a 4096 KB (4 MB) ROM chip. 270 271config UBOOT_ROMSIZE_KB_8192 272 bool "8192 KB (8 MB)" 273 help 274 Choose this option if you have a 8192 KB (8 MB) ROM chip. 275 276config UBOOT_ROMSIZE_KB_16384 277 bool "16384 KB (16 MB)" 278 help 279 Choose this option if you have a 16384 KB (16 MB) ROM chip. 280 281endchoice 282 283# Map the config names to an integer (KB). 284config UBOOT_ROMSIZE_KB 285 int 286 default 512 if UBOOT_ROMSIZE_KB_512 287 default 1024 if UBOOT_ROMSIZE_KB_1024 288 default 2048 if UBOOT_ROMSIZE_KB_2048 289 default 4096 if UBOOT_ROMSIZE_KB_4096 290 default 8192 if UBOOT_ROMSIZE_KB_8192 291 default 16384 if UBOOT_ROMSIZE_KB_16384 292 293# Map the config names to a hex value (bytes). 294config ROM_SIZE 295 hex 296 default 0x80000 if UBOOT_ROMSIZE_KB_512 297 default 0x100000 if UBOOT_ROMSIZE_KB_1024 298 default 0x200000 if UBOOT_ROMSIZE_KB_2048 299 default 0x400000 if UBOOT_ROMSIZE_KB_4096 300 default 0x800000 if UBOOT_ROMSIZE_KB_8192 301 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 302 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 303 304config HAVE_INTEL_ME 305 bool "Platform requires Intel Management Engine" 306 help 307 Newer higher-end devices have an Intel Management Engine (ME) 308 which is a very large binary blob (typically 1.5MB) which is 309 required for the platform to work. This enforces a particular 310 SPI flash format. You will need to supply the me.bin file in 311 your board directory. 312 313config X86_RAMTEST 314 bool "Perform a simple RAM test after SDRAM initialisation" 315 help 316 If there is something wrong with SDRAM then the platform will 317 often crash within U-Boot or the kernel. This option enables a 318 very simple RAM test that quickly checks whether the SDRAM seems 319 to work correctly. It is not exhaustive but can save time by 320 detecting obvious failures. 321 322config FLASH_DESCRIPTOR_FILE 323 string "Flash descriptor binary filename" 324 depends on HAVE_INTEL_ME 325 default "descriptor.bin" 326 help 327 The filename of the file to use as flash descriptor in the 328 board directory. 329 330config INTEL_ME_FILE 331 string "Intel Management Engine binary filename" 332 depends on HAVE_INTEL_ME 333 default "me.bin" 334 help 335 The filename of the file to use as Intel Management Engine in the 336 board directory. 337 338config HAVE_FSP 339 bool "Add an Firmware Support Package binary" 340 depends on !EFI 341 help 342 Select this option to add an Firmware Support Package binary to 343 the resulting U-Boot image. It is a binary blob which U-Boot uses 344 to set up SDRAM and other chipset specific initialization. 345 346 Note: Without this binary U-Boot will not be able to set up its 347 SDRAM so will not boot. 348 349config FSP_FILE 350 string "Firmware Support Package binary filename" 351 depends on HAVE_FSP 352 default "fsp.bin" 353 help 354 The filename of the file to use as Firmware Support Package binary 355 in the board directory. 356 357config FSP_ADDR 358 hex "Firmware Support Package binary location" 359 depends on HAVE_FSP 360 default 0xfffc0000 361 help 362 FSP is not Position Independent Code (PIC) and the whole FSP has to 363 be rebased if it is placed at a location which is different from the 364 perferred base address specified during the FSP build. Use Intel's 365 Binary Configuration Tool (BCT) to do the rebase. 366 367 The default base address of 0xfffc0000 indicates that the binary must 368 be located at offset 0xc0000 from the beginning of a 1MB flash device. 369 370config FSP_TEMP_RAM_ADDR 371 hex 372 depends on HAVE_FSP 373 default 0x2000000 374 help 375 Stack top address which is used in fsp_init() after DRAM is ready and 376 CAR is disabled. 377 378config FSP_SYS_MALLOC_F_LEN 379 hex 380 depends on HAVE_FSP 381 default 0x100000 382 help 383 Additional size of malloc() pool before relocation. 384 385config FSP_USE_UPD 386 bool 387 depends on HAVE_FSP 388 default y 389 help 390 Most FSPs use UPD data region for some FSP customization. But there 391 are still some FSPs that might not even have UPD. For such FSPs, 392 override this to n in their platform Kconfig files. 393 394config FSP_BROKEN_HOB 395 bool 396 depends on HAVE_FSP 397 help 398 Indicate some buggy FSPs that does not report memory used by FSP 399 itself as reserved in the resource descriptor HOB. Select this to 400 tell U-Boot to do some additional work to ensure U-Boot relocation 401 do not overwrite the important boot service data which is used by 402 FSP, otherwise the subsequent call to fsp_notify() will fail. 403 404config FSP_LOCKDOWN_SPI 405 bool 406 depends on HAVE_FSP 407 help 408 Some Intel FSP (like Braswell) does SPI lock-down during the call 409 to fsp_notify(INIT_PHASE_BOOT). This option should be turned on 410 for such FSP and U-Boot will configure the SPI opcode registers 411 before the lock-down. 412 413config ENABLE_MRC_CACHE 414 bool "Enable MRC cache" 415 depends on !EFI && !SYS_COREBOOT 416 help 417 Enable this feature to cause MRC data to be cached in NV storage 418 to be used for speeding up boot time on future reboots and/or 419 power cycles. 420 421 For platforms that use Intel FSP for the memory initialization, 422 please check FSP output HOB via U-Boot command 'fsp hob' to see 423 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 424 If such GUID does not exist, MRC cache is not avaiable on such 425 platform (eg: Intel Queensbay), which means selecting this option 426 here does not make any difference. 427 428config HAVE_MRC 429 bool "Add a System Agent binary" 430 depends on !HAVE_FSP 431 help 432 Select this option to add a System Agent binary to 433 the resulting U-Boot image. MRC stands for Memory Reference Code. 434 It is a binary blob which U-Boot uses to set up SDRAM. 435 436 Note: Without this binary U-Boot will not be able to set up its 437 SDRAM so will not boot. 438 439config CACHE_MRC_BIN 440 bool 441 depends on HAVE_MRC 442 default n 443 help 444 Enable caching for the memory reference code binary. This uses an 445 MTRR (memory type range register) to turn on caching for the section 446 of SPI flash that contains the memory reference code. This makes 447 SDRAM init run faster. 448 449config CACHE_MRC_SIZE_KB 450 int 451 depends on HAVE_MRC 452 default 512 453 help 454 Sets the size of the cached area for the memory reference code. 455 This ends at the end of SPI flash (address 0xffffffff) and is 456 measured in KB. Typically this is set to 512, providing for 0.5MB 457 of cached space. 458 459config DCACHE_RAM_BASE 460 hex 461 depends on HAVE_MRC 462 help 463 Sets the base of the data cache area in memory space. This is the 464 start address of the cache-as-RAM (CAR) area and the address varies 465 depending on the CPU. Once CAR is set up, read/write memory becomes 466 available at this address and can be used temporarily until SDRAM 467 is working. 468 469config DCACHE_RAM_SIZE 470 hex 471 depends on HAVE_MRC 472 default 0x40000 473 help 474 Sets the total size of the data cache area in memory space. This 475 sets the size of the cache-as-RAM (CAR) area. Note that much of the 476 CAR space is required by the MRC. The CAR space available to U-Boot 477 is normally at the start and typically extends to 1/4 or 1/2 of the 478 available size. 479 480config DCACHE_RAM_MRC_VAR_SIZE 481 hex 482 depends on HAVE_MRC 483 help 484 This is the amount of CAR (Cache as RAM) reserved for use by the 485 memory reference code. This depends on the implementation of the 486 memory reference code and must be set correctly or the board will 487 not boot. 488 489config HAVE_REFCODE 490 bool "Add a Reference Code binary" 491 help 492 Select this option to add a Reference Code binary to the resulting 493 U-Boot image. This is an Intel binary blob that handles system 494 initialisation, in this case the PCH and System Agent. 495 496 Note: Without this binary (on platforms that need it such as 497 broadwell) U-Boot will be missing some critical setup steps. 498 Various peripherals may fail to work. 499 500config SMP 501 bool "Enable Symmetric Multiprocessing" 502 default n 503 help 504 Enable use of more than one CPU in U-Boot and the Operating System 505 when loaded. Each CPU will be started up and information can be 506 obtained using the 'cpu' command. If this option is disabled, then 507 only one CPU will be enabled regardless of the number of CPUs 508 available. 509 510config MAX_CPUS 511 int "Maximum number of CPUs permitted" 512 depends on SMP 513 default 4 514 help 515 When using multi-CPU chips it is possible for U-Boot to start up 516 more than one CPU. The stack memory used by all of these CPUs is 517 pre-allocated so at present U-Boot wants to know the maximum 518 number of CPUs that may be present. Set this to at least as high 519 as the number of CPUs in your system (it uses about 4KB of RAM for 520 each CPU). 521 522config AP_STACK_SIZE 523 hex 524 depends on SMP 525 default 0x1000 526 help 527 Each additional CPU started by U-Boot requires its own stack. This 528 option sets the stack size used by each CPU and directly affects 529 the memory used by this initialisation process. Typically 4KB is 530 enough space. 531 532config HAVE_VGA_BIOS 533 bool "Add a VGA BIOS image" 534 help 535 Select this option if you have a VGA BIOS image that you would 536 like to add to your ROM. 537 538config VGA_BIOS_FILE 539 string "VGA BIOS image filename" 540 depends on HAVE_VGA_BIOS 541 default "vga.bin" 542 help 543 The filename of the VGA BIOS image in the board directory. 544 545config VGA_BIOS_ADDR 546 hex "VGA BIOS image location" 547 depends on HAVE_VGA_BIOS 548 default 0xfff90000 549 help 550 The location of VGA BIOS image in the SPI flash. For example, base 551 address of 0xfff90000 indicates that the image will be put at offset 552 0x90000 from the beginning of a 1MB flash device. 553 554config ROM_TABLE_ADDR 555 hex 556 default 0xf0000 557 help 558 All x86 tables happen to like the address range from 0x0f0000 559 to 0x100000. We use 0xf0000 as the starting address to store 560 those tables, including PIRQ routing table, Multi-Processor 561 table and ACPI table. 562 563config ROM_TABLE_SIZE 564 hex 565 default 0x10000 566 567menu "System tables" 568 depends on !EFI && !SYS_COREBOOT 569 570config GENERATE_PIRQ_TABLE 571 bool "Generate a PIRQ table" 572 default n 573 help 574 Generate a PIRQ routing table for this board. The PIRQ routing table 575 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 576 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 577 It specifies the interrupt router information as well how all the PCI 578 devices' interrupt pins are wired to PIRQs. 579 580config GENERATE_SFI_TABLE 581 bool "Generate a SFI (Simple Firmware Interface) table" 582 help 583 The Simple Firmware Interface (SFI) provides a lightweight method 584 for platform firmware to pass information to the operating system 585 via static tables in memory. Kernel SFI support is required to 586 boot on SFI-only platforms. If you have ACPI tables then these are 587 used instead. 588 589 U-Boot writes this table in write_sfi_table() just before booting 590 the OS. 591 592 For more information, see http://simplefirmware.org 593 594config GENERATE_MP_TABLE 595 bool "Generate an MP (Multi-Processor) table" 596 default n 597 help 598 Generate an MP (Multi-Processor) table for this board. The MP table 599 provides a way for the operating system to support for symmetric 600 multiprocessing as well as symmetric I/O interrupt handling with 601 the local APIC and I/O APIC. 602 603config GENERATE_ACPI_TABLE 604 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 605 default n 606 select QFW if QEMU 607 help 608 The Advanced Configuration and Power Interface (ACPI) specification 609 provides an open standard for device configuration and management 610 by the operating system. It defines platform-independent interfaces 611 for configuration and power management monitoring. 612 613endmenu 614 615config HAVE_ACPI_RESUME 616 bool "Enable ACPI S3 resume" 617 help 618 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping 619 state where all system context is lost except system memory. U-Boot 620 is responsible for restoring the machine state as it was before sleep. 621 It needs restore the memory controller, without overwriting memory 622 which is not marked as reserved. For the peripherals which lose their 623 registers, U-Boot needs to write the original value. When everything 624 is done, U-Boot needs to find out the wakeup vector provided by OSes 625 and jump there. 626 627config S3_VGA_ROM_RUN 628 bool "Re-run VGA option ROMs on S3 resume" 629 depends on HAVE_ACPI_RESUME 630 default y if HAVE_ACPI_RESUME 631 help 632 Execute VGA option ROMs in U-Boot when resuming from S3. Normally 633 this is needed when graphics console is being used in the kernel. 634 635 Turning it off can reduce some resume time, but be aware that your 636 graphics console won't work without VGA options ROMs. Set it to N 637 if your kernel is only on a serial console. 638 639config STACK_SIZE 640 hex 641 depends on HAVE_ACPI_RESUME 642 default 0x1000 643 help 644 Estimated U-Boot's runtime stack size that needs to be reserved 645 during an ACPI S3 resume. 646 647config MAX_PIRQ_LINKS 648 int 649 default 8 650 help 651 This variable specifies the number of PIRQ interrupt links which are 652 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 653 Some newer chipsets offer more than four links, commonly up to PIRQH. 654 655config IRQ_SLOT_COUNT 656 int 657 default 128 658 help 659 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 660 which in turns forms a table of exact 4KiB. The default value 128 661 should be enough for most boards. If this does not fit your board, 662 change it according to your needs. 663 664config PCIE_ECAM_BASE 665 hex 666 default 0xe0000000 667 help 668 This is the memory-mapped address of PCI configuration space, which 669 is only available through the Enhanced Configuration Access 670 Mechanism (ECAM) with PCI Express. It can be set up almost 671 anywhere. Before it is set up, it is possible to access PCI 672 configuration space through I/O access, but memory access is more 673 convenient. Using this, PCI can be scanned and configured. This 674 should be set to a region that does not conflict with memory 675 assigned to PCI devices - i.e. the memory and prefetch regions, as 676 passed to pci_set_region(). 677 678config PCIE_ECAM_SIZE 679 hex 680 default 0x10000000 681 help 682 This is the size of memory-mapped address of PCI configuration space, 683 which is only available through the Enhanced Configuration Access 684 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 685 so a default 0x10000000 size covers all of the 256 buses which is the 686 maximum number of PCI buses as defined by the PCI specification. 687 688config I8259_PIC 689 bool 690 default y 691 help 692 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 693 slave) interrupt controllers. Include this to have U-Boot set up 694 the interrupt correctly. 695 696config I8254_TIMER 697 bool 698 default y 699 help 700 Intel 8254 timer contains three counters which have fixed uses. 701 Include this to have U-Boot set up the timer correctly. 702 703config SEABIOS 704 bool "Support booting SeaBIOS" 705 help 706 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 707 It can run in an emulator or natively on X86 hardware with the use 708 of coreboot/U-Boot. By turning on this option, U-Boot prepares 709 all the configuration tables that are necessary to boot SeaBIOS. 710 711 Check http://www.seabios.org/SeaBIOS for details. 712 713config HIGH_TABLE_SIZE 714 hex "Size of configuration tables which reside in high memory" 715 default 0x10000 716 depends on SEABIOS 717 help 718 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 719 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 720 puts a copy of configuration tables in high memory region which 721 is reserved on the stack before relocation. The region size is 722 determined by this option. 723 724 Increse it if the default size does not fit the board's needs. 725 This is most likely due to a large ACPI DSDT table is used. 726 727source "arch/x86/lib/efi/Kconfig" 728 729endmenu 730