xref: /openbmc/u-boot/arch/x86/Kconfig (revision 4bb656e9)
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7choice
8	prompt "Mainboard vendor"
9	default VENDOR_EMULATION
10
11config VENDOR_CONGATEC
12	bool "congatec"
13
14config VENDOR_COREBOOT
15	bool "coreboot"
16
17config VENDOR_EFI
18	bool "efi"
19
20config VENDOR_EMULATION
21	bool "emulation"
22
23config VENDOR_GOOGLE
24	bool "Google"
25
26config VENDOR_INTEL
27	bool "Intel"
28
29endchoice
30
31# board-specific options below
32source "board/congatec/Kconfig"
33source "board/coreboot/Kconfig"
34source "board/efi/Kconfig"
35source "board/emulation/Kconfig"
36source "board/google/Kconfig"
37source "board/intel/Kconfig"
38
39# platform-specific options below
40source "arch/x86/cpu/baytrail/Kconfig"
41source "arch/x86/cpu/broadwell/Kconfig"
42source "arch/x86/cpu/coreboot/Kconfig"
43source "arch/x86/cpu/ivybridge/Kconfig"
44source "arch/x86/cpu/qemu/Kconfig"
45source "arch/x86/cpu/quark/Kconfig"
46source "arch/x86/cpu/queensbay/Kconfig"
47
48# architecture-specific options below
49
50config SYS_MALLOC_F_LEN
51	default 0x800
52
53config RAMBASE
54	hex
55	default 0x100000
56
57config XIP_ROM_SIZE
58	hex
59	depends on X86_RESET_VECTOR
60	default ROM_SIZE
61
62config CPU_ADDR_BITS
63	int
64	default 36
65
66config HPET_ADDRESS
67	hex
68	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
69
70config SMM_TSEG
71	bool
72	default n
73
74config SMM_TSEG_SIZE
75	hex
76
77config X86_RESET_VECTOR
78	bool
79	default n
80
81config RESET_SEG_START
82	hex
83	depends on X86_RESET_VECTOR
84	default 0xffff0000
85
86config RESET_SEG_SIZE
87	hex
88	depends on X86_RESET_VECTOR
89	default 0x10000
90
91config RESET_VEC_LOC
92	hex
93	depends on X86_RESET_VECTOR
94	default 0xfffffff0
95
96config SYS_X86_START16
97	hex
98	depends on X86_RESET_VECTOR
99	default 0xfffff800
100
101config BOARD_ROMSIZE_KB_512
102	bool
103config BOARD_ROMSIZE_KB_1024
104	bool
105config BOARD_ROMSIZE_KB_2048
106	bool
107config BOARD_ROMSIZE_KB_4096
108	bool
109config BOARD_ROMSIZE_KB_8192
110	bool
111config BOARD_ROMSIZE_KB_16384
112	bool
113
114choice
115	prompt "ROM chip size"
116	depends on X86_RESET_VECTOR
117	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
118	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
119	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
120	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
121	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
122	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
123	help
124	  Select the size of the ROM chip you intend to flash U-Boot on.
125
126	  The build system will take care of creating a u-boot.rom file
127	  of the matching size.
128
129config UBOOT_ROMSIZE_KB_512
130	bool "512 KB"
131	help
132	  Choose this option if you have a 512 KB ROM chip.
133
134config UBOOT_ROMSIZE_KB_1024
135	bool "1024 KB (1 MB)"
136	help
137	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
138
139config UBOOT_ROMSIZE_KB_2048
140	bool "2048 KB (2 MB)"
141	help
142	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
143
144config UBOOT_ROMSIZE_KB_4096
145	bool "4096 KB (4 MB)"
146	help
147	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
148
149config UBOOT_ROMSIZE_KB_8192
150	bool "8192 KB (8 MB)"
151	help
152	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
153
154config UBOOT_ROMSIZE_KB_16384
155	bool "16384 KB (16 MB)"
156	help
157	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
158
159endchoice
160
161# Map the config names to an integer (KB).
162config UBOOT_ROMSIZE_KB
163	int
164	default 512 if UBOOT_ROMSIZE_KB_512
165	default 1024 if UBOOT_ROMSIZE_KB_1024
166	default 2048 if UBOOT_ROMSIZE_KB_2048
167	default 4096 if UBOOT_ROMSIZE_KB_4096
168	default 8192 if UBOOT_ROMSIZE_KB_8192
169	default 16384 if UBOOT_ROMSIZE_KB_16384
170
171# Map the config names to a hex value (bytes).
172config ROM_SIZE
173	hex
174	default 0x80000 if UBOOT_ROMSIZE_KB_512
175	default 0x100000 if UBOOT_ROMSIZE_KB_1024
176	default 0x200000 if UBOOT_ROMSIZE_KB_2048
177	default 0x400000 if UBOOT_ROMSIZE_KB_4096
178	default 0x800000 if UBOOT_ROMSIZE_KB_8192
179	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
180	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
181
182config HAVE_INTEL_ME
183	bool "Platform requires Intel Management Engine"
184	help
185	  Newer higher-end devices have an Intel Management Engine (ME)
186	  which is a very large binary blob (typically 1.5MB) which is
187	  required for the platform to work. This enforces a particular
188	  SPI flash format. You will need to supply the me.bin file in
189	  your board directory.
190
191config X86_RAMTEST
192	bool "Perform a simple RAM test after SDRAM initialisation"
193	help
194	  If there is something wrong with SDRAM then the platform will
195	  often crash within U-Boot or the kernel. This option enables a
196	  very simple RAM test that quickly checks whether the SDRAM seems
197	  to work correctly. It is not exhaustive but can save time by
198	  detecting obvious failures.
199
200config HAVE_FSP
201	bool "Add an Firmware Support Package binary"
202	depends on !EFI
203	help
204	  Select this option to add an Firmware Support Package binary to
205	  the resulting U-Boot image. It is a binary blob which U-Boot uses
206	  to set up SDRAM and other chipset specific initialization.
207
208	  Note: Without this binary U-Boot will not be able to set up its
209	  SDRAM so will not boot.
210
211config FSP_FILE
212	string "Firmware Support Package binary filename"
213	depends on HAVE_FSP
214	default "fsp.bin"
215	help
216	  The filename of the file to use as Firmware Support Package binary
217	  in the board directory.
218
219config FSP_ADDR
220	hex "Firmware Support Package binary location"
221	depends on HAVE_FSP
222	default 0xfffc0000
223	help
224	  FSP is not Position Independent Code (PIC) and the whole FSP has to
225	  be rebased if it is placed at a location which is different from the
226	  perferred base address specified during the FSP build. Use Intel's
227	  Binary Configuration Tool (BCT) to do the rebase.
228
229	  The default base address of 0xfffc0000 indicates that the binary must
230	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
231
232config FSP_TEMP_RAM_ADDR
233	hex
234	depends on HAVE_FSP
235	default 0x2000000
236	help
237	  Stack top address which is used in fsp_init() after DRAM is ready and
238	  CAR is disabled.
239
240config FSP_SYS_MALLOC_F_LEN
241	hex
242	depends on HAVE_FSP
243	default 0x100000
244	help
245	  Additional size of malloc() pool before relocation.
246
247config FSP_USE_UPD
248	bool
249	depends on HAVE_FSP
250	default y
251	help
252	  Most FSPs use UPD data region for some FSP customization. But there
253	  are still some FSPs that might not even have UPD. For such FSPs,
254	  override this to n in their platform Kconfig files.
255
256config FSP_BROKEN_HOB
257	bool
258	depends on HAVE_FSP
259	help
260	  Indicate some buggy FSPs that does not report memory used by FSP
261	  itself as reserved in the resource descriptor HOB. Select this to
262	  tell U-Boot to do some additional work to ensure U-Boot relocation
263	  do not overwrite the important boot service data which is used by
264	  FSP, otherwise the subsequent call to fsp_notify() will fail.
265
266config ENABLE_MRC_CACHE
267	bool "Enable MRC cache"
268	depends on !EFI && !SYS_COREBOOT
269	help
270	  Enable this feature to cause MRC data to be cached in NV storage
271	  to be used for speeding up boot time on future reboots and/or
272	  power cycles.
273
274config HAVE_MRC
275	bool "Add a System Agent binary"
276	depends on !HAVE_FSP
277	help
278	  Select this option to add a System Agent binary to
279	  the resulting U-Boot image. MRC stands for Memory Reference Code.
280	  It is a binary blob which U-Boot uses to set up SDRAM.
281
282	  Note: Without this binary U-Boot will not be able to set up its
283	  SDRAM so will not boot.
284
285config CACHE_MRC_BIN
286	bool
287	depends on HAVE_MRC
288	default n
289	help
290	  Enable caching for the memory reference code binary. This uses an
291	  MTRR (memory type range register) to turn on caching for the section
292	  of SPI flash that contains the memory reference code. This makes
293	  SDRAM init run faster.
294
295config CACHE_MRC_SIZE_KB
296	int
297	depends on HAVE_MRC
298	default 512
299	help
300	  Sets the size of the cached area for the memory reference code.
301	  This ends at the end of SPI flash (address 0xffffffff) and is
302	  measured in KB. Typically this is set to 512, providing for 0.5MB
303	  of cached space.
304
305config DCACHE_RAM_BASE
306	hex
307	depends on HAVE_MRC
308	help
309	  Sets the base of the data cache area in memory space. This is the
310	  start address of the cache-as-RAM (CAR) area and the address varies
311	  depending on the CPU. Once CAR is set up, read/write memory becomes
312	  available at this address and can be used temporarily until SDRAM
313	  is working.
314
315config DCACHE_RAM_SIZE
316	hex
317	depends on HAVE_MRC
318	default 0x40000
319	help
320	  Sets the total size of the data cache area in memory space. This
321	  sets the size of the cache-as-RAM (CAR) area. Note that much of the
322	  CAR space is required by the MRC. The CAR space available to U-Boot
323	  is normally at the start and typically extends to 1/4 or 1/2 of the
324	  available size.
325
326config DCACHE_RAM_MRC_VAR_SIZE
327	hex
328	depends on HAVE_MRC
329	help
330	  This is the amount of CAR (Cache as RAM) reserved for use by the
331	  memory reference code. This depends on the implementation of the
332	  memory reference code and must be set correctly or the board will
333	  not boot.
334
335config HAVE_REFCODE
336        bool "Add a Reference Code binary"
337        help
338          Select this option to add a Reference Code binary to the resulting
339          U-Boot image. This is an Intel binary blob that handles system
340          initialisation, in this case the PCH and System Agent.
341
342          Note: Without this binary (on platforms that need it such as
343          broadwell) U-Boot will be missing some critical setup steps.
344          Various peripherals may fail to work.
345
346config SMP
347	bool "Enable Symmetric Multiprocessing"
348	default n
349	help
350	  Enable use of more than one CPU in U-Boot and the Operating System
351	  when loaded. Each CPU will be started up and information can be
352	  obtained using the 'cpu' command. If this option is disabled, then
353	  only one CPU will be enabled regardless of the number of CPUs
354	  available.
355
356config MAX_CPUS
357	int "Maximum number of CPUs permitted"
358	depends on SMP
359	default 4
360	help
361	  When using multi-CPU chips it is possible for U-Boot to start up
362	  more than one CPU. The stack memory used by all of these CPUs is
363	  pre-allocated so at present U-Boot wants to know the maximum
364	  number of CPUs that may be present. Set this to at least as high
365	  as the number of CPUs in your system (it uses about 4KB of RAM for
366	  each CPU).
367
368config AP_STACK_SIZE
369	hex
370	depends on SMP
371	default 0x1000
372	help
373	  Each additional CPU started by U-Boot requires its own stack. This
374	  option sets the stack size used by each CPU and directly affects
375	  the memory used by this initialisation process. Typically 4KB is
376	  enough space.
377
378config HAVE_VGA_BIOS
379	bool "Add a VGA BIOS image"
380	help
381	  Select this option if you have a VGA BIOS image that you would
382	  like to add to your ROM.
383
384config VGA_BIOS_FILE
385	string "VGA BIOS image filename"
386	depends on HAVE_VGA_BIOS
387	default "vga.bin"
388	help
389	  The filename of the VGA BIOS image in the board directory.
390
391config VGA_BIOS_ADDR
392	hex "VGA BIOS image location"
393	depends on HAVE_VGA_BIOS
394	default 0xfff90000
395	help
396	  The location of VGA BIOS image in the SPI flash. For example, base
397	  address of 0xfff90000 indicates that the image will be put at offset
398	  0x90000 from the beginning of a 1MB flash device.
399
400menu "System tables"
401	depends on !EFI && !SYS_COREBOOT
402
403config GENERATE_PIRQ_TABLE
404	bool "Generate a PIRQ table"
405	default n
406	help
407	  Generate a PIRQ routing table for this board. The PIRQ routing table
408	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
409	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
410	  It specifies the interrupt router information as well how all the PCI
411	  devices' interrupt pins are wired to PIRQs.
412
413config GENERATE_SFI_TABLE
414	bool "Generate a SFI (Simple Firmware Interface) table"
415	help
416	  The Simple Firmware Interface (SFI) provides a lightweight method
417	  for platform firmware to pass information to the operating system
418	  via static tables in memory.  Kernel SFI support is required to
419	  boot on SFI-only platforms.  If you have ACPI tables then these are
420	  used instead.
421
422	  U-Boot writes this table in write_sfi_table() just before booting
423	  the OS.
424
425	  For more information, see http://simplefirmware.org
426
427config GENERATE_MP_TABLE
428	bool "Generate an MP (Multi-Processor) table"
429	default n
430	help
431	  Generate an MP (Multi-Processor) table for this board. The MP table
432	  provides a way for the operating system to support for symmetric
433	  multiprocessing as well as symmetric I/O interrupt handling with
434	  the local APIC and I/O APIC.
435
436config GENERATE_ACPI_TABLE
437	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
438	default n
439	help
440	  The Advanced Configuration and Power Interface (ACPI) specification
441	  provides an open standard for device configuration and management
442	  by the operating system. It defines platform-independent interfaces
443	  for configuration and power management monitoring.
444
445config QEMU_ACPI_TABLE
446	bool "Load ACPI table from QEMU fw_cfg interface"
447	depends on GENERATE_ACPI_TABLE && QEMU
448	default y
449	help
450	  By default, U-Boot generates its own ACPI tables. This option, if
451	  enabled, disables U-Boot's version and loads ACPI tables generated
452	  by QEMU.
453
454config GENERATE_SMBIOS_TABLE
455	bool "Generate an SMBIOS (System Management BIOS) table"
456	default y
457	help
458	  The System Management BIOS (SMBIOS) specification addresses how
459	  motherboard and system vendors present management information about
460	  their products in a standard format by extending the BIOS interface
461	  on Intel architecture systems.
462
463	  Check http://www.dmtf.org/standards/smbios for details.
464
465endmenu
466
467config MAX_PIRQ_LINKS
468	int
469	default 8
470	help
471	  This variable specifies the number of PIRQ interrupt links which are
472	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
473	  Some newer chipsets offer more than four links, commonly up to PIRQH.
474
475config IRQ_SLOT_COUNT
476	int
477	default 128
478	help
479	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
480	  which in turns forms a table of exact 4KiB. The default value 128
481	  should be enough for most boards. If this does not fit your board,
482	  change it according to your needs.
483
484config PCIE_ECAM_BASE
485	hex
486	default 0xe0000000
487	help
488	  This is the memory-mapped address of PCI configuration space, which
489	  is only available through the Enhanced Configuration Access
490	  Mechanism (ECAM) with PCI Express. It can be set up almost
491	  anywhere. Before it is set up, it is possible to access PCI
492	  configuration space through I/O access, but memory access is more
493	  convenient. Using this, PCI can be scanned and configured. This
494	  should be set to a region that does not conflict with memory
495	  assigned to PCI devices - i.e. the memory and prefetch regions, as
496	  passed to pci_set_region().
497
498config PCIE_ECAM_SIZE
499	hex
500	default 0x10000000
501	help
502	  This is the size of memory-mapped address of PCI configuration space,
503	  which is only available through the Enhanced Configuration Access
504	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
505	  so a default 0x10000000 size covers all of the 256 buses which is the
506	  maximum number of PCI buses as defined by the PCI specification.
507
508config I8259_PIC
509	bool
510	default y
511	help
512	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
513	  slave) interrupt controllers. Include this to have U-Boot set up
514	  the interrupt correctly.
515
516config I8254_TIMER
517	bool
518	default y
519	help
520	  Intel 8254 timer contains three counters which have fixed uses.
521	  Include this to have U-Boot set up the timer correctly.
522
523config I8042_KEYB
524	default y
525
526config DM_KEYBOARD
527	default y
528
529config SEABIOS
530	bool "Support booting SeaBIOS"
531	help
532	  SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
533	  It can run in an emulator or natively on X86 hardware with the use
534	  of coreboot/U-Boot. By turning on this option, U-Boot prepares
535	  all the configuration tables that are necessary to boot SeaBIOS.
536
537	  Check http://www.seabios.org/SeaBIOS for details.
538
539source "arch/x86/lib/efi/Kconfig"
540
541endmenu
542