xref: /openbmc/u-boot/arch/x86/Kconfig (revision 3dcdd17b) 
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7choice
8	prompt "Mainboard vendor"
9	default VENDOR_EMULATION
10
11config VENDOR_COREBOOT
12	bool "coreboot"
13
14config VENDOR_EFI
15	bool "efi"
16
17config VENDOR_EMULATION
18	bool "emulation"
19
20config VENDOR_GOOGLE
21	bool "Google"
22
23config VENDOR_INTEL
24	bool "Intel"
25
26endchoice
27
28# board-specific options below
29source "board/coreboot/Kconfig"
30source "board/emulation/Kconfig"
31source "board/google/Kconfig"
32source "board/intel/Kconfig"
33
34# platform-specific options below
35source "arch/x86/cpu/baytrail/Kconfig"
36source "arch/x86/cpu/coreboot/Kconfig"
37source "arch/x86/cpu/ivybridge/Kconfig"
38source "arch/x86/cpu/qemu/Kconfig"
39source "arch/x86/cpu/quark/Kconfig"
40source "arch/x86/cpu/queensbay/Kconfig"
41
42# architecture-specific options below
43
44config SYS_MALLOC_F_LEN
45	default 0x800
46
47config RAMBASE
48	hex
49	default 0x100000
50
51config XIP_ROM_SIZE
52	hex
53	depends on X86_RESET_VECTOR
54	default ROM_SIZE
55
56config CPU_ADDR_BITS
57	int
58	default 36
59
60config HPET_ADDRESS
61	hex
62	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
63
64config SMM_TSEG
65	bool
66	default n
67
68config SMM_TSEG_SIZE
69	hex
70
71config X86_RESET_VECTOR
72	bool
73	default n
74
75config RESET_SEG_START
76	hex
77	depends on X86_RESET_VECTOR
78	default 0xffff0000
79
80config RESET_SEG_SIZE
81	hex
82	depends on X86_RESET_VECTOR
83	default 0x10000
84
85config RESET_VEC_LOC
86	hex
87	depends on X86_RESET_VECTOR
88	default 0xfffffff0
89
90config SYS_X86_START16
91	hex
92	depends on X86_RESET_VECTOR
93	default 0xfffff800
94
95config BOARD_ROMSIZE_KB_512
96	bool
97config BOARD_ROMSIZE_KB_1024
98	bool
99config BOARD_ROMSIZE_KB_2048
100	bool
101config BOARD_ROMSIZE_KB_4096
102	bool
103config BOARD_ROMSIZE_KB_8192
104	bool
105config BOARD_ROMSIZE_KB_16384
106	bool
107
108choice
109	prompt "ROM chip size"
110	depends on X86_RESET_VECTOR
111	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
112	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
113	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
114	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
115	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
116	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
117	help
118	  Select the size of the ROM chip you intend to flash U-Boot on.
119
120	  The build system will take care of creating a u-boot.rom file
121	  of the matching size.
122
123config UBOOT_ROMSIZE_KB_512
124	bool "512 KB"
125	help
126	  Choose this option if you have a 512 KB ROM chip.
127
128config UBOOT_ROMSIZE_KB_1024
129	bool "1024 KB (1 MB)"
130	help
131	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
132
133config UBOOT_ROMSIZE_KB_2048
134	bool "2048 KB (2 MB)"
135	help
136	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
137
138config UBOOT_ROMSIZE_KB_4096
139	bool "4096 KB (4 MB)"
140	help
141	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
142
143config UBOOT_ROMSIZE_KB_8192
144	bool "8192 KB (8 MB)"
145	help
146	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
147
148config UBOOT_ROMSIZE_KB_16384
149	bool "16384 KB (16 MB)"
150	help
151	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
152
153endchoice
154
155# Map the config names to an integer (KB).
156config UBOOT_ROMSIZE_KB
157	int
158	default 512 if UBOOT_ROMSIZE_KB_512
159	default 1024 if UBOOT_ROMSIZE_KB_1024
160	default 2048 if UBOOT_ROMSIZE_KB_2048
161	default 4096 if UBOOT_ROMSIZE_KB_4096
162	default 8192 if UBOOT_ROMSIZE_KB_8192
163	default 16384 if UBOOT_ROMSIZE_KB_16384
164
165# Map the config names to a hex value (bytes).
166config ROM_SIZE
167	hex
168	default 0x80000 if UBOOT_ROMSIZE_KB_512
169	default 0x100000 if UBOOT_ROMSIZE_KB_1024
170	default 0x200000 if UBOOT_ROMSIZE_KB_2048
171	default 0x400000 if UBOOT_ROMSIZE_KB_4096
172	default 0x800000 if UBOOT_ROMSIZE_KB_8192
173	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
174	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
175
176config HAVE_INTEL_ME
177	bool "Platform requires Intel Management Engine"
178	help
179	  Newer higher-end devices have an Intel Management Engine (ME)
180	  which is a very large binary blob (typically 1.5MB) which is
181	  required for the platform to work. This enforces a particular
182	  SPI flash format. You will need to supply the me.bin file in
183	  your board directory.
184
185config X86_RAMTEST
186	bool "Perform a simple RAM test after SDRAM initialisation"
187	help
188	  If there is something wrong with SDRAM then the platform will
189	  often crash within U-Boot or the kernel. This option enables a
190	  very simple RAM test that quickly checks whether the SDRAM seems
191	  to work correctly. It is not exhaustive but can save time by
192	  detecting obvious failures.
193
194config HAVE_FSP
195	bool "Add an Firmware Support Package binary"
196	help
197	  Select this option to add an Firmware Support Package binary to
198	  the resulting U-Boot image. It is a binary blob which U-Boot uses
199	  to set up SDRAM and other chipset specific initialization.
200
201	  Note: Without this binary U-Boot will not be able to set up its
202	  SDRAM so will not boot.
203
204config FSP_FILE
205	string "Firmware Support Package binary filename"
206	depends on HAVE_FSP
207	default "fsp.bin"
208	help
209	  The filename of the file to use as Firmware Support Package binary
210	  in the board directory.
211
212config FSP_ADDR
213	hex "Firmware Support Package binary location"
214	depends on HAVE_FSP
215	default 0xfffc0000
216	help
217	  FSP is not Position Independent Code (PIC) and the whole FSP has to
218	  be rebased if it is placed at a location which is different from the
219	  perferred base address specified during the FSP build. Use Intel's
220	  Binary Configuration Tool (BCT) to do the rebase.
221
222	  The default base address of 0xfffc0000 indicates that the binary must
223	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
224
225config FSP_TEMP_RAM_ADDR
226	hex
227	depends on HAVE_FSP
228	default 0x2000000
229	help
230	  Stack top address which is used in FspInit after DRAM is ready and
231	  CAR is disabled.
232
233config SMP
234	bool "Enable Symmetric Multiprocessing"
235	default n
236	help
237	  Enable use of more than one CPU in U-Boot and the Operating System
238	  when loaded. Each CPU will be started up and information can be
239	  obtained using the 'cpu' command. If this option is disabled, then
240	  only one CPU will be enabled regardless of the number of CPUs
241	  available.
242
243config MAX_CPUS
244	int "Maximum number of CPUs permitted"
245	depends on SMP
246	default 4
247	help
248	  When using multi-CPU chips it is possible for U-Boot to start up
249	  more than one CPU. The stack memory used by all of these CPUs is
250	  pre-allocated so at present U-Boot wants to know the maximum
251	  number of CPUs that may be present. Set this to at least as high
252	  as the number of CPUs in your system (it uses about 4KB of RAM for
253	  each CPU).
254
255config AP_STACK_SIZE
256	hex
257	depends on SMP
258	default 0x1000
259	help
260	  Each additional CPU started by U-Boot requires its own stack. This
261	  option sets the stack size used by each CPU and directly affects
262	  the memory used by this initialisation process. Typically 4KB is
263	  enough space.
264
265config TSC_CALIBRATION_BYPASS
266	bool "Bypass Time-Stamp Counter (TSC) calibration"
267	default n
268	help
269	  By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
270	  running frequency via Model-Specific Register (MSR) and Programmable
271	  Interval Timer (PIT). If the calibration does not work on your board,
272	  select this option and provide a hardcoded TSC running frequency with
273	  CONFIG_TSC_FREQ_IN_MHZ below.
274
275	  Normally this option should be turned on in a simulation environment
276	  like qemu.
277
278config TSC_FREQ_IN_MHZ
279	int "Time-Stamp Counter (TSC) running frequency in MHz"
280	depends on TSC_CALIBRATION_BYPASS
281	default 1000
282	help
283	  The running frequency in MHz of Time-Stamp Counter (TSC).
284
285config HAVE_VGA_BIOS
286	bool "Add a VGA BIOS image"
287	help
288	  Select this option if you have a VGA BIOS image that you would
289	  like to add to your ROM.
290
291config VGA_BIOS_FILE
292	string "VGA BIOS image filename"
293	depends on HAVE_VGA_BIOS
294	default "vga.bin"
295	help
296	  The filename of the VGA BIOS image in the board directory.
297
298config VGA_BIOS_ADDR
299	hex "VGA BIOS image location"
300	depends on HAVE_VGA_BIOS
301	default 0xfff90000
302	help
303	  The location of VGA BIOS image in the SPI flash. For example, base
304	  address of 0xfff90000 indicates that the image will be put at offset
305	  0x90000 from the beginning of a 1MB flash device.
306
307menu "System tables"
308
309config GENERATE_PIRQ_TABLE
310	bool "Generate a PIRQ table"
311	default n
312	help
313	  Generate a PIRQ routing table for this board. The PIRQ routing table
314	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
315	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
316	  It specifies the interrupt router information as well how all the PCI
317	  devices' interrupt pins are wired to PIRQs.
318
319config GENERATE_SFI_TABLE
320	bool "Generate a SFI (Simple Firmware Interface) table"
321	help
322	  The Simple Firmware Interface (SFI) provides a lightweight method
323	  for platform firmware to pass information to the operating system
324	  via static tables in memory.  Kernel SFI support is required to
325	  boot on SFI-only platforms.  If you have ACPI tables then these are
326	  used instead.
327
328	  U-Boot writes this table in write_sfi_table() just before booting
329	  the OS.
330
331	  For more information, see http://simplefirmware.org
332
333config GENERATE_MP_TABLE
334	bool "Generate an MP (Multi-Processor) table"
335	default n
336	help
337	  Generate an MP (Multi-Processor) table for this board. The MP table
338	  provides a way for the operating system to support for symmetric
339	  multiprocessing as well as symmetric I/O interrupt handling with
340	  the local APIC and I/O APIC.
341
342endmenu
343
344config MAX_PIRQ_LINKS
345	int
346	default 8
347	help
348	  This variable specifies the number of PIRQ interrupt links which are
349	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
350	  Some newer chipsets offer more than four links, commonly up to PIRQH.
351
352config IRQ_SLOT_COUNT
353	int
354	default 128
355	help
356	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
357	  which in turns forms a table of exact 4KiB. The default value 128
358	  should be enough for most boards. If this does not fit your board,
359	  change it according to your needs.
360
361config PCIE_ECAM_BASE
362	hex
363	default 0xe0000000
364	help
365	  This is the memory-mapped address of PCI configuration space, which
366	  is only available through the Enhanced Configuration Access
367	  Mechanism (ECAM) with PCI Express. It can be set up almost
368	  anywhere. Before it is set up, it is possible to access PCI
369	  configuration space through I/O access, but memory access is more
370	  convenient. Using this, PCI can be scanned and configured. This
371	  should be set to a region that does not conflict with memory
372	  assigned to PCI devices - i.e. the memory and prefetch regions, as
373	  passed to pci_set_region().
374
375config PCIE_ECAM_SIZE
376	hex
377	default 0x10000000
378	help
379	  This is the size of memory-mapped address of PCI configuration space,
380	  which is only available through the Enhanced Configuration Access
381	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
382	  so a default 0x10000000 size covers all of the 256 buses which is the
383	  maximum number of PCI buses as defined by the PCI specification.
384
385endmenu
386