1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Mainboard vendor" 9 default VENDOR_EMULATION 10 11config VENDOR_COREBOOT 12 bool "coreboot" 13 14config VENDOR_EMULATION 15 bool "emulation" 16 17config VENDOR_GOOGLE 18 bool "Google" 19 20config VENDOR_INTEL 21 bool "Intel" 22 23endchoice 24 25# board-specific options below 26source "board/coreboot/Kconfig" 27source "board/emulation/Kconfig" 28source "board/google/Kconfig" 29source "board/intel/Kconfig" 30 31# platform-specific options below 32source "arch/x86/cpu/baytrail/Kconfig" 33source "arch/x86/cpu/coreboot/Kconfig" 34source "arch/x86/cpu/ivybridge/Kconfig" 35source "arch/x86/cpu/qemu/Kconfig" 36source "arch/x86/cpu/quark/Kconfig" 37source "arch/x86/cpu/queensbay/Kconfig" 38 39# architecture-specific options below 40 41config SYS_MALLOC_F_LEN 42 default 0x800 43 44config RAMBASE 45 hex 46 default 0x100000 47 48config XIP_ROM_SIZE 49 hex 50 depends on X86_RESET_VECTOR 51 default ROM_SIZE 52 53config CPU_ADDR_BITS 54 int 55 default 36 56 57config HPET_ADDRESS 58 hex 59 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 60 61config SMM_TSEG 62 bool 63 default n 64 65config SMM_TSEG_SIZE 66 hex 67 68config X86_RESET_VECTOR 69 bool 70 default n 71 72config RESET_SEG_START 73 hex 74 depends on X86_RESET_VECTOR 75 default 0xffff0000 76 77config RESET_SEG_SIZE 78 hex 79 depends on X86_RESET_VECTOR 80 default 0x10000 81 82config RESET_VEC_LOC 83 hex 84 depends on X86_RESET_VECTOR 85 default 0xfffffff0 86 87config SYS_X86_START16 88 hex 89 depends on X86_RESET_VECTOR 90 default 0xfffff800 91 92config BOARD_ROMSIZE_KB_512 93 bool 94config BOARD_ROMSIZE_KB_1024 95 bool 96config BOARD_ROMSIZE_KB_2048 97 bool 98config BOARD_ROMSIZE_KB_4096 99 bool 100config BOARD_ROMSIZE_KB_8192 101 bool 102config BOARD_ROMSIZE_KB_16384 103 bool 104 105choice 106 prompt "ROM chip size" 107 depends on X86_RESET_VECTOR 108 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 109 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 110 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 111 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 112 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 113 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 114 help 115 Select the size of the ROM chip you intend to flash U-Boot on. 116 117 The build system will take care of creating a u-boot.rom file 118 of the matching size. 119 120config UBOOT_ROMSIZE_KB_512 121 bool "512 KB" 122 help 123 Choose this option if you have a 512 KB ROM chip. 124 125config UBOOT_ROMSIZE_KB_1024 126 bool "1024 KB (1 MB)" 127 help 128 Choose this option if you have a 1024 KB (1 MB) ROM chip. 129 130config UBOOT_ROMSIZE_KB_2048 131 bool "2048 KB (2 MB)" 132 help 133 Choose this option if you have a 2048 KB (2 MB) ROM chip. 134 135config UBOOT_ROMSIZE_KB_4096 136 bool "4096 KB (4 MB)" 137 help 138 Choose this option if you have a 4096 KB (4 MB) ROM chip. 139 140config UBOOT_ROMSIZE_KB_8192 141 bool "8192 KB (8 MB)" 142 help 143 Choose this option if you have a 8192 KB (8 MB) ROM chip. 144 145config UBOOT_ROMSIZE_KB_16384 146 bool "16384 KB (16 MB)" 147 help 148 Choose this option if you have a 16384 KB (16 MB) ROM chip. 149 150endchoice 151 152# Map the config names to an integer (KB). 153config UBOOT_ROMSIZE_KB 154 int 155 default 512 if UBOOT_ROMSIZE_KB_512 156 default 1024 if UBOOT_ROMSIZE_KB_1024 157 default 2048 if UBOOT_ROMSIZE_KB_2048 158 default 4096 if UBOOT_ROMSIZE_KB_4096 159 default 8192 if UBOOT_ROMSIZE_KB_8192 160 default 16384 if UBOOT_ROMSIZE_KB_16384 161 162# Map the config names to a hex value (bytes). 163config ROM_SIZE 164 hex 165 default 0x80000 if UBOOT_ROMSIZE_KB_512 166 default 0x100000 if UBOOT_ROMSIZE_KB_1024 167 default 0x200000 if UBOOT_ROMSIZE_KB_2048 168 default 0x400000 if UBOOT_ROMSIZE_KB_4096 169 default 0x800000 if UBOOT_ROMSIZE_KB_8192 170 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 171 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 172 173config HAVE_INTEL_ME 174 bool "Platform requires Intel Management Engine" 175 help 176 Newer higher-end devices have an Intel Management Engine (ME) 177 which is a very large binary blob (typically 1.5MB) which is 178 required for the platform to work. This enforces a particular 179 SPI flash format. You will need to supply the me.bin file in 180 your board directory. 181 182config X86_RAMTEST 183 bool "Perform a simple RAM test after SDRAM initialisation" 184 help 185 If there is something wrong with SDRAM then the platform will 186 often crash within U-Boot or the kernel. This option enables a 187 very simple RAM test that quickly checks whether the SDRAM seems 188 to work correctly. It is not exhaustive but can save time by 189 detecting obvious failures. 190 191config MARK_GRAPHICS_MEM_WRCOMB 192 bool "Mark graphics memory as write-combining" 193 default n 194 help 195 The graphics performance may increase if the graphics 196 memory is set as write-combining cache type. This option 197 enables marking the graphics memory as write-combining. 198 199config HAVE_FSP 200 bool "Add an Firmware Support Package binary" 201 help 202 Select this option to add an Firmware Support Package binary to 203 the resulting U-Boot image. It is a binary blob which U-Boot uses 204 to set up SDRAM and other chipset specific initialization. 205 206 Note: Without this binary U-Boot will not be able to set up its 207 SDRAM so will not boot. 208 209config FSP_FILE 210 string "Firmware Support Package binary filename" 211 depends on HAVE_FSP 212 default "fsp.bin" 213 help 214 The filename of the file to use as Firmware Support Package binary 215 in the board directory. 216 217config FSP_ADDR 218 hex "Firmware Support Package binary location" 219 depends on HAVE_FSP 220 default 0xfffc0000 221 help 222 FSP is not Position Independent Code (PIC) and the whole FSP has to 223 be rebased if it is placed at a location which is different from the 224 perferred base address specified during the FSP build. Use Intel's 225 Binary Configuration Tool (BCT) to do the rebase. 226 227 The default base address of 0xfffc0000 indicates that the binary must 228 be located at offset 0xc0000 from the beginning of a 1MB flash device. 229 230config FSP_TEMP_RAM_ADDR 231 hex 232 depends on HAVE_FSP 233 default 0x2000000 234 help 235 Stack top address which is used in FspInit after DRAM is ready and 236 CAR is disabled. 237 238config MAX_CPUS 239 int "Maximum number of CPUs permitted" 240 default 4 241 help 242 When using multi-CPU chips it is possible for U-Boot to start up 243 more than one CPU. The stack memory used by all of these CPUs is 244 pre-allocated so at present U-Boot wants to know the maximum 245 number of CPUs that may be present. Set this to at least as high 246 as the number of CPUs in your system (it uses about 4KB of RAM for 247 each CPU). 248 249config SMP 250 bool "Enable Symmetric Multiprocessing" 251 default n 252 help 253 Enable use of more than one CPU in U-Boot and the Operating System 254 when loaded. Each CPU will be started up and information can be 255 obtained using the 'cpu' command. If this option is disabled, then 256 only one CPU will be enabled regardless of the number of CPUs 257 available. 258 259config AP_STACK_SIZE 260 hex 261 default 0x1000 262 help 263 Each additional CPU started by U-Boot requires its own stack. This 264 option sets the stack size used by each CPU and directly affects 265 the memory used by this initialisation process. Typically 4KB is 266 enough space. 267 268config TSC_CALIBRATION_BYPASS 269 bool "Bypass Time-Stamp Counter (TSC) calibration" 270 default n 271 help 272 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 273 running frequency via Model-Specific Register (MSR) and Programmable 274 Interval Timer (PIT). If the calibration does not work on your board, 275 select this option and provide a hardcoded TSC running frequency with 276 CONFIG_TSC_FREQ_IN_MHZ below. 277 278 Normally this option should be turned on in a simulation environment 279 like qemu. 280 281config TSC_FREQ_IN_MHZ 282 int "Time-Stamp Counter (TSC) running frequency in MHz" 283 depends on TSC_CALIBRATION_BYPASS 284 default 1000 285 help 286 The running frequency in MHz of Time-Stamp Counter (TSC). 287 288menu "System tables" 289 290config GENERATE_PIRQ_TABLE 291 bool "Generate a PIRQ table" 292 default n 293 help 294 Generate a PIRQ routing table for this board. The PIRQ routing table 295 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 296 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 297 It specifies the interrupt router information as well how all the PCI 298 devices' interrupt pins are wired to PIRQs. 299 300config GENERATE_SFI_TABLE 301 bool "Generate a SFI (Simple Firmware Interface) table" 302 help 303 The Simple Firmware Interface (SFI) provides a lightweight method 304 for platform firmware to pass information to the operating system 305 via static tables in memory. Kernel SFI support is required to 306 boot on SFI-only platforms. If you have ACPI tables then these are 307 used instead. 308 309 U-Boot writes this table in write_sfi_table() just before booting 310 the OS. 311 312 For more information, see http://simplefirmware.org 313 314endmenu 315 316config MAX_PIRQ_LINKS 317 int 318 default 8 319 help 320 This variable specifies the number of PIRQ interrupt links which are 321 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 322 Some newer chipsets offer more than four links, commonly up to PIRQH. 323 324config IRQ_SLOT_COUNT 325 int 326 default 128 327 help 328 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 329 which in turns forms a table of exact 4KiB. The default value 128 330 should be enough for most boards. If this does not fit your board, 331 change it according to your needs. 332 333config PCIE_ECAM_BASE 334 hex 335 default 0xe0000000 336 help 337 This is the memory-mapped address of PCI configuration space, which 338 is only available through the Enhanced Configuration Access 339 Mechanism (ECAM) with PCI Express. It can be set up almost 340 anywhere. Before it is set up, it is possible to access PCI 341 configuration space through I/O access, but memory access is more 342 convenient. Using this, PCI can be scanned and configured. This 343 should be set to a region that does not conflict with memory 344 assigned to PCI devices - i.e. the memory and prefetch regions, as 345 passed to pci_set_region(). 346 347endmenu 348