1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7config USE_PRIVATE_LIBGCC 8 default y 9 10choice 11 prompt "Target select" 12 13config TARGET_COREBOOT 14 bool "Support coreboot" 15 help 16 This target is used for running U-Boot on top of Coreboot. In 17 this case Coreboot does the early inititalisation, and U-Boot 18 takes over once the RAM, video and CPU are fully running. 19 U-Boot is loaded as a fallback payload from Coreboot, in 20 Coreboot terminology. This method was used for the Chromebook 21 Pixel when launched. 22 23config TARGET_CHROMEBOOK_LINK 24 bool "Support Chromebook link" 25 help 26 This is the Chromebook Pixel released in 2013. It uses an Intel 27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of 28 SDRAM. It has a Panther Point platform controller hub, PCIe 29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD 30 reader, microphone and speakers, display port and 32GB SATA 31 solid state drive. There is a Chrome OS EC connected on LPC, 32 and it provides a 2560x1700 high resolution touch-enabled LCD 33 display. 34 35config TARGET_CROWNBAY 36 bool "Support Intel Crown Bay CRB" 37 help 38 This is the Intel Crown Bay Customer Reference Board. It contains 39 the Intel Atom Processor E6xx populated on the COM Express module 40 with 1GB DDR2 soldered down memory and a carrier board with the 41 Intel Platform Controller Hub EG20T, other system components and 42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. 43 44config TARGET_MINNOWMAX 45 bool "Support Intel Minnowboard MAX" 46 help 47 This is the Intel Minnowboard MAX. It contains an Atom E3800 48 processor in a small form factor with Ethernet, micro-SD, USB 2, 49 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. 50 It requires some binary blobs - see README.x86 for details. 51 52 Note that PCIE_ECAM_BASE is set up by the FSP so the value used 53 by U-Boot matches that value. 54 55config TARGET_GALILEO 56 bool "Support Intel Galileo" 57 help 58 This is the Intel Galileo board, which is the first in a family of 59 Arduino-certified development and prototyping boards based on Intel 60 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit 61 single-core, single-thread, Intel Pentium processor instrunction set 62 architecture (ISA) compatible, operating at speeds up to 400Mhz, 63 along with 256MB DDR3 memory. It supports a wide range of industry 64 standard I/O interfaces, including a full-sized mini-PCIe slot, 65 one 100Mb Ethernet port, a microSD card slot, a USB host port and 66 a USB client port. 67 68endchoice 69 70config DM 71 default y 72 73config DM_GPIO 74 default y 75 76config DM_SERIAL 77 default y 78 79config RAMBASE 80 hex 81 default 0x100000 82 83config XIP_ROM_SIZE 84 hex 85 depends on X86_RESET_VECTOR 86 default ROM_SIZE 87 88config CPU_ADDR_BITS 89 int 90 default 36 91 92config HPET_ADDRESS 93 hex 94 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 95 96config SMM_TSEG 97 bool 98 default n 99 100config SMM_TSEG_SIZE 101 hex 102 103config X86_RESET_VECTOR 104 bool 105 default n 106 107config SYS_X86_START16 108 hex 109 depends on X86_RESET_VECTOR 110 default 0xfffff800 111 112config BOARD_ROMSIZE_KB_512 113 bool 114config BOARD_ROMSIZE_KB_1024 115 bool 116config BOARD_ROMSIZE_KB_2048 117 bool 118config BOARD_ROMSIZE_KB_4096 119 bool 120config BOARD_ROMSIZE_KB_8192 121 bool 122config BOARD_ROMSIZE_KB_16384 123 bool 124 125choice 126 prompt "ROM chip size" 127 depends on X86_RESET_VECTOR 128 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 129 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 130 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 131 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 132 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 133 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 134 help 135 Select the size of the ROM chip you intend to flash U-Boot on. 136 137 The build system will take care of creating a u-boot.rom file 138 of the matching size. 139 140config UBOOT_ROMSIZE_KB_512 141 bool "512 KB" 142 help 143 Choose this option if you have a 512 KB ROM chip. 144 145config UBOOT_ROMSIZE_KB_1024 146 bool "1024 KB (1 MB)" 147 help 148 Choose this option if you have a 1024 KB (1 MB) ROM chip. 149 150config UBOOT_ROMSIZE_KB_2048 151 bool "2048 KB (2 MB)" 152 help 153 Choose this option if you have a 2048 KB (2 MB) ROM chip. 154 155config UBOOT_ROMSIZE_KB_4096 156 bool "4096 KB (4 MB)" 157 help 158 Choose this option if you have a 4096 KB (4 MB) ROM chip. 159 160config UBOOT_ROMSIZE_KB_8192 161 bool "8192 KB (8 MB)" 162 help 163 Choose this option if you have a 8192 KB (8 MB) ROM chip. 164 165config UBOOT_ROMSIZE_KB_16384 166 bool "16384 KB (16 MB)" 167 help 168 Choose this option if you have a 16384 KB (16 MB) ROM chip. 169 170endchoice 171 172# Map the config names to an integer (KB). 173config UBOOT_ROMSIZE_KB 174 int 175 default 512 if UBOOT_ROMSIZE_KB_512 176 default 1024 if UBOOT_ROMSIZE_KB_1024 177 default 2048 if UBOOT_ROMSIZE_KB_2048 178 default 4096 if UBOOT_ROMSIZE_KB_4096 179 default 8192 if UBOOT_ROMSIZE_KB_8192 180 default 16384 if UBOOT_ROMSIZE_KB_16384 181 182# Map the config names to a hex value (bytes). 183config ROM_SIZE 184 hex 185 default 0x80000 if UBOOT_ROMSIZE_KB_512 186 default 0x100000 if UBOOT_ROMSIZE_KB_1024 187 default 0x200000 if UBOOT_ROMSIZE_KB_2048 188 default 0x400000 if UBOOT_ROMSIZE_KB_4096 189 default 0x800000 if UBOOT_ROMSIZE_KB_8192 190 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 191 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 192 193config HAVE_INTEL_ME 194 bool "Platform requires Intel Management Engine" 195 help 196 Newer higher-end devices have an Intel Management Engine (ME) 197 which is a very large binary blob (typically 1.5MB) which is 198 required for the platform to work. This enforces a particular 199 SPI flash format. You will need to supply the me.bin file in 200 your board directory. 201 202config X86_RAMTEST 203 bool "Perform a simple RAM test after SDRAM initialisation" 204 help 205 If there is something wrong with SDRAM then the platform will 206 often crash within U-Boot or the kernel. This option enables a 207 very simple RAM test that quickly checks whether the SDRAM seems 208 to work correctly. It is not exhaustive but can save time by 209 detecting obvious failures. 210 211config MARK_GRAPHICS_MEM_WRCOMB 212 bool "Mark graphics memory as write-combining." 213 default n 214 help 215 The graphics performance may increase if the graphics 216 memory is set as write-combining cache type. This option 217 enables marking the graphics memory as write-combining. 218 219menu "Display" 220 221config FRAMEBUFFER_SET_VESA_MODE 222 prompt "Set framebuffer graphics resolution" 223 bool 224 help 225 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) 226 227choice 228 prompt "framebuffer graphics resolution" 229 default FRAMEBUFFER_VESA_MODE_117 230 depends on FRAMEBUFFER_SET_VESA_MODE 231 help 232 This option sets the resolution used for the coreboot framebuffer (and 233 bootsplash screen). 234 235config FRAMEBUFFER_VESA_MODE_100 236 bool "640x400 256-color" 237 238config FRAMEBUFFER_VESA_MODE_101 239 bool "640x480 256-color" 240 241config FRAMEBUFFER_VESA_MODE_102 242 bool "800x600 16-color" 243 244config FRAMEBUFFER_VESA_MODE_103 245 bool "800x600 256-color" 246 247config FRAMEBUFFER_VESA_MODE_104 248 bool "1024x768 16-color" 249 250config FRAMEBUFFER_VESA_MODE_105 251 bool "1024x7686 256-color" 252 253config FRAMEBUFFER_VESA_MODE_106 254 bool "1280x1024 16-color" 255 256config FRAMEBUFFER_VESA_MODE_107 257 bool "1280x1024 256-color" 258 259config FRAMEBUFFER_VESA_MODE_108 260 bool "80x60 text" 261 262config FRAMEBUFFER_VESA_MODE_109 263 bool "132x25 text" 264 265config FRAMEBUFFER_VESA_MODE_10A 266 bool "132x43 text" 267 268config FRAMEBUFFER_VESA_MODE_10B 269 bool "132x50 text" 270 271config FRAMEBUFFER_VESA_MODE_10C 272 bool "132x60 text" 273 274config FRAMEBUFFER_VESA_MODE_10D 275 bool "320x200 32k-color (1:5:5:5)" 276 277config FRAMEBUFFER_VESA_MODE_10E 278 bool "320x200 64k-color (5:6:5)" 279 280config FRAMEBUFFER_VESA_MODE_10F 281 bool "320x200 16.8M-color (8:8:8)" 282 283config FRAMEBUFFER_VESA_MODE_110 284 bool "640x480 32k-color (1:5:5:5)" 285 286config FRAMEBUFFER_VESA_MODE_111 287 bool "640x480 64k-color (5:6:5)" 288 289config FRAMEBUFFER_VESA_MODE_112 290 bool "640x480 16.8M-color (8:8:8)" 291 292config FRAMEBUFFER_VESA_MODE_113 293 bool "800x600 32k-color (1:5:5:5)" 294 295config FRAMEBUFFER_VESA_MODE_114 296 bool "800x600 64k-color (5:6:5)" 297 298config FRAMEBUFFER_VESA_MODE_115 299 bool "800x600 16.8M-color (8:8:8)" 300 301config FRAMEBUFFER_VESA_MODE_116 302 bool "1024x768 32k-color (1:5:5:5)" 303 304config FRAMEBUFFER_VESA_MODE_117 305 bool "1024x768 64k-color (5:6:5)" 306 307config FRAMEBUFFER_VESA_MODE_118 308 bool "1024x768 16.8M-color (8:8:8)" 309 310config FRAMEBUFFER_VESA_MODE_119 311 bool "1280x1024 32k-color (1:5:5:5)" 312 313config FRAMEBUFFER_VESA_MODE_11A 314 bool "1280x1024 64k-color (5:6:5)" 315 316config FRAMEBUFFER_VESA_MODE_11B 317 bool "1280x1024 16.8M-color (8:8:8)" 318 319config FRAMEBUFFER_VESA_MODE_USER 320 bool "Manually select VESA mode" 321 322endchoice 323 324# Map the config names to an integer (KB). 325config FRAMEBUFFER_VESA_MODE 326 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER 327 hex 328 default 0x100 if FRAMEBUFFER_VESA_MODE_100 329 default 0x101 if FRAMEBUFFER_VESA_MODE_101 330 default 0x102 if FRAMEBUFFER_VESA_MODE_102 331 default 0x103 if FRAMEBUFFER_VESA_MODE_103 332 default 0x104 if FRAMEBUFFER_VESA_MODE_104 333 default 0x105 if FRAMEBUFFER_VESA_MODE_105 334 default 0x106 if FRAMEBUFFER_VESA_MODE_106 335 default 0x107 if FRAMEBUFFER_VESA_MODE_107 336 default 0x108 if FRAMEBUFFER_VESA_MODE_108 337 default 0x109 if FRAMEBUFFER_VESA_MODE_109 338 default 0x10A if FRAMEBUFFER_VESA_MODE_10A 339 default 0x10B if FRAMEBUFFER_VESA_MODE_10B 340 default 0x10C if FRAMEBUFFER_VESA_MODE_10C 341 default 0x10D if FRAMEBUFFER_VESA_MODE_10D 342 default 0x10E if FRAMEBUFFER_VESA_MODE_10E 343 default 0x10F if FRAMEBUFFER_VESA_MODE_10F 344 default 0x110 if FRAMEBUFFER_VESA_MODE_110 345 default 0x111 if FRAMEBUFFER_VESA_MODE_111 346 default 0x112 if FRAMEBUFFER_VESA_MODE_112 347 default 0x113 if FRAMEBUFFER_VESA_MODE_113 348 default 0x114 if FRAMEBUFFER_VESA_MODE_114 349 default 0x115 if FRAMEBUFFER_VESA_MODE_115 350 default 0x116 if FRAMEBUFFER_VESA_MODE_116 351 default 0x117 if FRAMEBUFFER_VESA_MODE_117 352 default 0x118 if FRAMEBUFFER_VESA_MODE_118 353 default 0x119 if FRAMEBUFFER_VESA_MODE_119 354 default 0x11A if FRAMEBUFFER_VESA_MODE_11A 355 default 0x11B if FRAMEBUFFER_VESA_MODE_11B 356 default 0x117 if FRAMEBUFFER_VESA_MODE_USER 357 358endmenu 359 360config HAVE_FSP 361 bool "Add an Firmware Support Package binary" 362 help 363 Select this option to add an Firmware Support Package binary to 364 the resulting U-Boot image. It is a binary blob which U-Boot uses 365 to set up SDRAM and other chipset specific initialization. 366 367 Note: Without this binary U-Boot will not be able to set up its 368 SDRAM so will not boot. 369 370config FSP_FILE 371 string "Firmware Support Package binary filename" 372 depends on HAVE_FSP 373 default "fsp.bin" 374 help 375 The filename of the file to use as Firmware Support Package binary 376 in the board directory. 377 378config FSP_ADDR 379 hex "Firmware Support Package binary location" 380 depends on HAVE_FSP 381 default 0xfffc0000 382 help 383 FSP is not Position Independent Code (PIC) and the whole FSP has to 384 be rebased if it is placed at a location which is different from the 385 perferred base address specified during the FSP build. Use Intel's 386 Binary Configuration Tool (BCT) to do the rebase. 387 388 The default base address of 0xfffc0000 indicates that the binary must 389 be located at offset 0xc0000 from the beginning of a 1MB flash device. 390 391config FSP_TEMP_RAM_ADDR 392 hex 393 default 0x2000000 394 help 395 Stack top address which is used in FspInit after DRAM is ready and 396 CAR is disabled. 397 398source "arch/x86/cpu/baytrail/Kconfig" 399 400source "arch/x86/cpu/coreboot/Kconfig" 401 402source "arch/x86/cpu/ivybridge/Kconfig" 403 404source "arch/x86/cpu/quark/Kconfig" 405 406source "arch/x86/cpu/queensbay/Kconfig" 407 408config TSC_CALIBRATION_BYPASS 409 bool "Bypass Time-Stamp Counter (TSC) calibration" 410 default n 411 help 412 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 413 running frequency via Model-Specific Register (MSR) and Programmable 414 Interval Timer (PIT). If the calibration does not work on your board, 415 select this option and provide a hardcoded TSC running frequency with 416 CONFIG_TSC_FREQ_IN_MHZ below. 417 418 Normally this option should be turned on in a simulation environment 419 like qemu. 420 421config TSC_FREQ_IN_MHZ 422 int "Time-Stamp Counter (TSC) running frequency in MHz" 423 depends on TSC_CALIBRATION_BYPASS 424 default 1000 425 help 426 The running frequency in MHz of Time-Stamp Counter (TSC). 427 428source "board/coreboot/coreboot/Kconfig" 429 430source "board/google/chromebook_link/Kconfig" 431 432source "board/intel/crownbay/Kconfig" 433 434source "board/intel/minnowmax/Kconfig" 435 436source "board/intel/galileo/Kconfig" 437 438config PCIE_ECAM_BASE 439 hex 440 default 0xe0000000 441 help 442 This is the memory-mapped address of PCI configuration space, which 443 is only available through the Enhanced Configuration Access 444 Mechanism (ECAM) with PCI Express. It can be set up almost 445 anywhere. Before it is set up, it is possible to access PCI 446 configuration space through I/O access, but memory access is more 447 convenient. Using this, PCI can be scanned and configured. This 448 should be set to a region that does not conflict with memory 449 assigned to PCI devices - i.e. the memory and prefetch regions, as 450 passed to pci_set_region(). 451 452endmenu 453