1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Andes Technology Corporation 4 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 5 */ 6 7 #include <common.h> 8 9 void icache_enable(void) 10 { 11 #ifndef CONFIG_SYS_ICACHE_OFF 12 #ifdef CONFIG_RISCV_NDS 13 asm volatile ( 14 "csrr t1, mcache_ctl\n\t" 15 "ori t0, t1, 0x1\n\t" 16 "csrw mcache_ctl, t0\n\t" 17 ); 18 #endif 19 #endif 20 } 21 22 void icache_disable(void) 23 { 24 #ifndef CONFIG_SYS_ICACHE_OFF 25 #ifdef CONFIG_RISCV_NDS 26 asm volatile ( 27 "fence.i\n\t" 28 "csrr t1, mcache_ctl\n\t" 29 "andi t0, t1, ~0x1\n\t" 30 "csrw mcache_ctl, t0\n\t" 31 ); 32 #endif 33 #endif 34 } 35 36 void dcache_enable(void) 37 { 38 #ifndef CONFIG_SYS_DCACHE_OFF 39 #ifdef CONFIG_RISCV_NDS 40 asm volatile ( 41 "csrr t1, mcache_ctl\n\t" 42 "ori t0, t1, 0x2\n\t" 43 "csrw mcache_ctl, t0\n\t" 44 ); 45 #endif 46 #endif 47 } 48 49 void dcache_disable(void) 50 { 51 #ifndef CONFIG_SYS_DCACHE_OFF 52 #ifdef CONFIG_RISCV_NDS 53 asm volatile ( 54 "fence\n\t" 55 "csrr t1, mcache_ctl\n\t" 56 "andi t0, t1, ~0x2\n\t" 57 "csrw mcache_ctl, t0\n\t" 58 ); 59 #endif 60 #endif 61 } 62 63 int icache_status(void) 64 { 65 int ret = 0; 66 67 #ifdef CONFIG_RISCV_NDS 68 asm volatile ( 69 "csrr t1, mcache_ctl\n\t" 70 "andi %0, t1, 0x01\n\t" 71 : "=r" (ret) 72 : 73 : "memory" 74 ); 75 #endif 76 77 return ret; 78 } 79 80 int dcache_status(void) 81 { 82 int ret = 0; 83 84 #ifdef CONFIG_RISCV_NDS 85 asm volatile ( 86 "csrr t1, mcache_ctl\n\t" 87 "andi %0, t1, 0x02\n\t" 88 : "=r" (ret) 89 : 90 : "memory" 91 ); 92 #endif 93 94 return ret; 95 } 96