1dd1033e4SGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2dd1033e4SGregory CLEMENT /* 3dd1033e4SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4dd1033e4SGregory CLEMENT */ 5dd1033e4SGregory CLEMENT 6dd1033e4SGregory CLEMENT #include <common.h> 7dd1033e4SGregory CLEMENT 8dd1033e4SGregory CLEMENT #include <asm/sections.h> 9dd1033e4SGregory CLEMENT #include <asm/io.h> 10dd1033e4SGregory CLEMENT 11dd1033e4SGregory CLEMENT #include <asm/reboot.h> 12dd1033e4SGregory CLEMENT 13dd1033e4SGregory CLEMENT void _machine_restart(void) 14dd1033e4SGregory CLEMENT { 15*e7a0de2cSHoratiu Vultur #if defined(CONFIG_SOC_JR2) 16*e7a0de2cSHoratiu Vultur register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); 17*e7a0de2cSHoratiu Vultur /* Set owner */ 18*e7a0de2cSHoratiu Vultur reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M; 19*e7a0de2cSHoratiu Vultur reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1); 20*e7a0de2cSHoratiu Vultur /* Set boot mode */ 21*e7a0de2cSHoratiu Vultur reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA; 22*e7a0de2cSHoratiu Vultur writel(reg, BASE_CFG + ICPU_GENERAL_CTRL); 23*e7a0de2cSHoratiu Vultur /* Read back in order to make BOOT mode setting active */ 24*e7a0de2cSHoratiu Vultur reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); 25*e7a0de2cSHoratiu Vultur /* Reset CPU only - still executing _here_. but from cache */ 26*e7a0de2cSHoratiu Vultur writel(readl(BASE_CFG + ICPU_RESET) | 27*e7a0de2cSHoratiu Vultur ICPU_RESET_CORE_RST_CPU_ONLY | 28*e7a0de2cSHoratiu Vultur ICPU_RESET_CORE_RST_FORCE, 29*e7a0de2cSHoratiu Vultur BASE_CFG + ICPU_RESET); 30*e7a0de2cSHoratiu Vultur #else 31dd1033e4SGregory CLEMENT register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; 32dd1033e4SGregory CLEMENT (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); 33dd1033e4SGregory CLEMENT 34dd1033e4SGregory CLEMENT /* Make sure VCore is NOT protected from reset */ 35dd1033e4SGregory CLEMENT clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT); 36dd1033e4SGregory CLEMENT 37dd1033e4SGregory CLEMENT /* Change to SPI bitbang for SPI reset workaround... */ 38dd1033e4SGregory CLEMENT writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | 39dd1033e4SGregory CLEMENT ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE); 40dd1033e4SGregory CLEMENT 41dd1033e4SGregory CLEMENT /* Do the global reset */ 42dd1033e4SGregory CLEMENT writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); 43*e7a0de2cSHoratiu Vultur #endif 44dd1033e4SGregory CLEMENT 45dd1033e4SGregory CLEMENT while (1) 46dd1033e4SGregory CLEMENT ; /* NOP */ 47dd1033e4SGregory CLEMENT } 48