1*dd1033e4SGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*dd1033e4SGregory CLEMENT /* 3*dd1033e4SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4*dd1033e4SGregory CLEMENT */ 5*dd1033e4SGregory CLEMENT 6*dd1033e4SGregory CLEMENT #include <common.h> 7*dd1033e4SGregory CLEMENT 8*dd1033e4SGregory CLEMENT #include <asm/sections.h> 9*dd1033e4SGregory CLEMENT #include <asm/io.h> 10*dd1033e4SGregory CLEMENT 11*dd1033e4SGregory CLEMENT #include <asm/reboot.h> 12*dd1033e4SGregory CLEMENT 13*dd1033e4SGregory CLEMENT void _machine_restart(void) 14*dd1033e4SGregory CLEMENT { 15*dd1033e4SGregory CLEMENT register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; 16*dd1033e4SGregory CLEMENT (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); 17*dd1033e4SGregory CLEMENT 18*dd1033e4SGregory CLEMENT /* Make sure VCore is NOT protected from reset */ 19*dd1033e4SGregory CLEMENT clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT); 20*dd1033e4SGregory CLEMENT 21*dd1033e4SGregory CLEMENT /* Change to SPI bitbang for SPI reset workaround... */ 22*dd1033e4SGregory CLEMENT writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | 23*dd1033e4SGregory CLEMENT ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE); 24*dd1033e4SGregory CLEMENT 25*dd1033e4SGregory CLEMENT /* Do the global reset */ 26*dd1033e4SGregory CLEMENT writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); 27*dd1033e4SGregory CLEMENT 28*dd1033e4SGregory CLEMENT while (1) 29*dd1033e4SGregory CLEMENT ; /* NOP */ 30*dd1033e4SGregory CLEMENT } 31