1dd1033e4SGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2dd1033e4SGregory CLEMENT /* 3dd1033e4SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4dd1033e4SGregory CLEMENT */ 5dd1033e4SGregory CLEMENT 6dd1033e4SGregory CLEMENT #include <common.h> 7dd1033e4SGregory CLEMENT 8dd1033e4SGregory CLEMENT #include <asm/sections.h> 9dd1033e4SGregory CLEMENT #include <asm/io.h> 10dd1033e4SGregory CLEMENT 11dd1033e4SGregory CLEMENT #include <asm/reboot.h> 12dd1033e4SGregory CLEMENT 13dd1033e4SGregory CLEMENT void _machine_restart(void) 14dd1033e4SGregory CLEMENT { 1505512517SHoratiu Vultur #if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT) 16e7a0de2cSHoratiu Vultur register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); 17e7a0de2cSHoratiu Vultur /* Set owner */ 18e7a0de2cSHoratiu Vultur reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M; 19e7a0de2cSHoratiu Vultur reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1); 20e7a0de2cSHoratiu Vultur /* Set boot mode */ 21e7a0de2cSHoratiu Vultur reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA; 22e7a0de2cSHoratiu Vultur writel(reg, BASE_CFG + ICPU_GENERAL_CTRL); 23e7a0de2cSHoratiu Vultur /* Read back in order to make BOOT mode setting active */ 24e7a0de2cSHoratiu Vultur reg = readl(BASE_CFG + ICPU_GENERAL_CTRL); 25e7a0de2cSHoratiu Vultur /* Reset CPU only - still executing _here_. but from cache */ 26e7a0de2cSHoratiu Vultur writel(readl(BASE_CFG + ICPU_RESET) | 27e7a0de2cSHoratiu Vultur ICPU_RESET_CORE_RST_CPU_ONLY | 28e7a0de2cSHoratiu Vultur ICPU_RESET_CORE_RST_FORCE, 29e7a0de2cSHoratiu Vultur BASE_CFG + ICPU_RESET); 30*1895b87eSHoratiu Vultur #elif defined(CONFIG_SOC_SERVAL) 31*1895b87eSHoratiu Vultur register unsigned long i; 32*1895b87eSHoratiu Vultur 33*1895b87eSHoratiu Vultur /* Prevent VCore-III from being reset with a global reset */ 34*1895b87eSHoratiu Vultur writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); 35*1895b87eSHoratiu Vultur 36*1895b87eSHoratiu Vultur /* Do global reset */ 37*1895b87eSHoratiu Vultur writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); 38*1895b87eSHoratiu Vultur 39*1895b87eSHoratiu Vultur for (i = 0; i < 1000; i++) 40*1895b87eSHoratiu Vultur ; 41*1895b87eSHoratiu Vultur 42*1895b87eSHoratiu Vultur /* Power down DDR for clean DDR re-training */ 43*1895b87eSHoratiu Vultur writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) | 44*1895b87eSHoratiu Vultur ICPU_MEMCTRL_CTRL_PWR_DOWN, 45*1895b87eSHoratiu Vultur BASE_CFG + ICPU_MEMCTRL_CTRL); 46*1895b87eSHoratiu Vultur 47*1895b87eSHoratiu Vultur while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) & 48*1895b87eSHoratiu Vultur ICPU_MEMCTRL_STAT_PWR_DOWN_ACK)) 49*1895b87eSHoratiu Vultur ; 50*1895b87eSHoratiu Vultur 51*1895b87eSHoratiu Vultur /* Reset VCore-III, only. */ 52*1895b87eSHoratiu Vultur writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET); 53*1895b87eSHoratiu Vultur #else /* Luton || Ocelot */ 54dd1033e4SGregory CLEMENT register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST; 55dd1033e4SGregory CLEMENT (void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST); 56dd1033e4SGregory CLEMENT 57dd1033e4SGregory CLEMENT /* Make sure VCore is NOT protected from reset */ 58dd1033e4SGregory CLEMENT clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT); 59dd1033e4SGregory CLEMENT 60dd1033e4SGregory CLEMENT /* Change to SPI bitbang for SPI reset workaround... */ 61dd1033e4SGregory CLEMENT writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) | 62dd1033e4SGregory CLEMENT ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE); 63dd1033e4SGregory CLEMENT 64dd1033e4SGregory CLEMENT /* Do the global reset */ 65dd1033e4SGregory CLEMENT writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST); 66e7a0de2cSHoratiu Vultur #endif 67dd1033e4SGregory CLEMENT 68dd1033e4SGregory CLEMENT while (1) 69dd1033e4SGregory CLEMENT ; /* NOP */ 70dd1033e4SGregory CLEMENT } 71