183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 230374f98SPaul Burton /* 330374f98SPaul Burton * (C) Copyright 2003 430374f98SPaul Burton * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 530374f98SPaul Burton */ 630374f98SPaul Burton 730374f98SPaul Burton #include <common.h> 830374f98SPaul Burton #include <asm/cacheops.h> 9939a255aSPaul Burton #ifdef CONFIG_MIPS_L2_CACHE 104baa0ab6SPaul Burton #include <asm/cm.h> 11939a255aSPaul Burton #endif 12219c2db3SPaul Burton #include <asm/io.h> 1330374f98SPaul Burton #include <asm/mipsregs.h> 14d8b32697SPaul Burton #include <asm/system.h> 1530374f98SPaul Burton 168cb4817dSPaul Burton DECLARE_GLOBAL_DATA_PTR; 1737228621SPaul Burton 184baa0ab6SPaul Burton static void probe_l2(void) 194baa0ab6SPaul Burton { 204baa0ab6SPaul Burton #ifdef CONFIG_MIPS_L2_CACHE 214baa0ab6SPaul Burton unsigned long conf2, sl; 224baa0ab6SPaul Burton bool l2c = false; 234baa0ab6SPaul Burton 244baa0ab6SPaul Burton if (!(read_c0_config1() & MIPS_CONF_M)) 254baa0ab6SPaul Burton return; 264baa0ab6SPaul Burton 274baa0ab6SPaul Burton conf2 = read_c0_config2(); 284baa0ab6SPaul Burton 294baa0ab6SPaul Burton if (__mips_isa_rev >= 6) { 304baa0ab6SPaul Burton l2c = conf2 & MIPS_CONF_M; 314baa0ab6SPaul Burton if (l2c) 324baa0ab6SPaul Burton l2c = read_c0_config3() & MIPS_CONF_M; 334baa0ab6SPaul Burton if (l2c) 344baa0ab6SPaul Burton l2c = read_c0_config4() & MIPS_CONF_M; 354baa0ab6SPaul Burton if (l2c) 364baa0ab6SPaul Burton l2c = read_c0_config5() & MIPS_CONF5_L2C; 374baa0ab6SPaul Burton } 384baa0ab6SPaul Burton 394baa0ab6SPaul Burton if (l2c && config_enabled(CONFIG_MIPS_CM)) { 404baa0ab6SPaul Burton gd->arch.l2_line_size = mips_cm_l2_line_size(); 414baa0ab6SPaul Burton } else if (l2c) { 424baa0ab6SPaul Burton /* We don't know how to retrieve L2 config on this system */ 434baa0ab6SPaul Burton BUG(); 444baa0ab6SPaul Burton } else { 454baa0ab6SPaul Burton sl = (conf2 & MIPS_CONF2_SL) >> MIPS_CONF2_SL_SHF; 464baa0ab6SPaul Burton gd->arch.l2_line_size = sl ? (2 << sl) : 0; 474baa0ab6SPaul Burton } 484baa0ab6SPaul Burton #endif 494baa0ab6SPaul Burton } 504baa0ab6SPaul Burton 518cb4817dSPaul Burton void mips_cache_probe(void) 528cb4817dSPaul Burton { 538cb4817dSPaul Burton #ifdef CONFIG_SYS_CACHE_SIZE_AUTO 548cb4817dSPaul Burton unsigned long conf1, il, dl; 5537228621SPaul Burton 5630374f98SPaul Burton conf1 = read_c0_config1(); 578cb4817dSPaul Burton 58a3ab2ae7SDaniel Schwierzeck il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF; 598cb4817dSPaul Burton dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF; 608cb4817dSPaul Burton 618cb4817dSPaul Burton gd->arch.l1i_line_size = il ? (2 << il) : 0; 628cb4817dSPaul Burton gd->arch.l1d_line_size = dl ? (2 << dl) : 0; 638cb4817dSPaul Burton #endif 644baa0ab6SPaul Burton probe_l2(); 658cb4817dSPaul Burton } 668cb4817dSPaul Burton 678cb4817dSPaul Burton static inline unsigned long icache_line_size(void) 688cb4817dSPaul Burton { 698cb4817dSPaul Burton #ifdef CONFIG_SYS_CACHE_SIZE_AUTO 708cb4817dSPaul Burton return gd->arch.l1i_line_size; 718cb4817dSPaul Burton #else 728cb4817dSPaul Burton return CONFIG_SYS_ICACHE_LINE_SIZE; 738cb4817dSPaul Burton #endif 7430374f98SPaul Burton } 7530374f98SPaul Burton 7630374f98SPaul Burton static inline unsigned long dcache_line_size(void) 7730374f98SPaul Burton { 788cb4817dSPaul Burton #ifdef CONFIG_SYS_CACHE_SIZE_AUTO 798cb4817dSPaul Burton return gd->arch.l1d_line_size; 808cb4817dSPaul Burton #else 8137228621SPaul Burton return CONFIG_SYS_DCACHE_LINE_SIZE; 828cb4817dSPaul Burton #endif 8330374f98SPaul Burton } 8430374f98SPaul Burton 854baa0ab6SPaul Burton static inline unsigned long scache_line_size(void) 864baa0ab6SPaul Burton { 874baa0ab6SPaul Burton #ifdef CONFIG_MIPS_L2_CACHE 884baa0ab6SPaul Burton return gd->arch.l2_line_size; 894baa0ab6SPaul Burton #else 904baa0ab6SPaul Burton return 0; 914baa0ab6SPaul Burton #endif 924baa0ab6SPaul Burton } 934baa0ab6SPaul Burton 94fb64cda5SPaul Burton #define cache_loop(start, end, lsize, ops...) do { \ 95fb64cda5SPaul Burton const void *addr = (const void *)(start & ~(lsize - 1)); \ 96fb64cda5SPaul Burton const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \ 97fb64cda5SPaul Burton const unsigned int cache_ops[] = { ops }; \ 98fb64cda5SPaul Burton unsigned int i; \ 99fb64cda5SPaul Burton \ 100cc4f3643SPaul Burton if (!lsize) \ 101cc4f3643SPaul Burton break; \ 102cc4f3643SPaul Burton \ 103fb64cda5SPaul Burton for (; addr <= aend; addr += lsize) { \ 104fb64cda5SPaul Burton for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \ 105fb64cda5SPaul Burton mips_cache(cache_ops[i], addr); \ 106fb64cda5SPaul Burton } \ 107fb64cda5SPaul Burton } while (0) 108fb64cda5SPaul Burton 10930374f98SPaul Burton void flush_cache(ulong start_addr, ulong size) 11030374f98SPaul Burton { 11130374f98SPaul Burton unsigned long ilsize = icache_line_size(); 11230374f98SPaul Burton unsigned long dlsize = dcache_line_size(); 1134baa0ab6SPaul Burton unsigned long slsize = scache_line_size(); 11430374f98SPaul Burton 11530374f98SPaul Burton /* aend will be miscalculated when size is zero, so we return here */ 11630374f98SPaul Burton if (size == 0) 11730374f98SPaul Burton return; 11830374f98SPaul Burton 1194baa0ab6SPaul Burton if ((ilsize == dlsize) && !slsize) { 12030374f98SPaul Burton /* flush I-cache & D-cache simultaneously */ 121fb64cda5SPaul Burton cache_loop(start_addr, start_addr + size, ilsize, 122fb64cda5SPaul Burton HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); 123219c2db3SPaul Burton goto ops_done; 12430374f98SPaul Burton } 12530374f98SPaul Burton 12630374f98SPaul Burton /* flush D-cache */ 127fb64cda5SPaul Burton cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); 12830374f98SPaul Burton 1294baa0ab6SPaul Burton /* flush L2 cache */ 130cc4f3643SPaul Burton cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); 1314baa0ab6SPaul Burton 13230374f98SPaul Burton /* flush I-cache */ 133fb64cda5SPaul Burton cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); 134219c2db3SPaul Burton 135219c2db3SPaul Burton ops_done: 136219c2db3SPaul Burton /* ensure cache ops complete before any further memory accesses */ 137219c2db3SPaul Burton sync(); 138d8b32697SPaul Burton 139d8b32697SPaul Burton /* ensure the pipeline doesn't contain now-invalid instructions */ 140d8b32697SPaul Burton instruction_hazard_barrier(); 14130374f98SPaul Burton } 14230374f98SPaul Burton 14330374f98SPaul Burton void flush_dcache_range(ulong start_addr, ulong stop) 14430374f98SPaul Burton { 14530374f98SPaul Burton unsigned long lsize = dcache_line_size(); 1464baa0ab6SPaul Burton unsigned long slsize = scache_line_size(); 14730374f98SPaul Burton 148fbb0de08SMarek Vasut /* aend will be miscalculated when size is zero, so we return here */ 149fbb0de08SMarek Vasut if (start_addr == stop) 150fbb0de08SMarek Vasut return; 151fbb0de08SMarek Vasut 152fb64cda5SPaul Burton cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); 1534baa0ab6SPaul Burton 1544baa0ab6SPaul Burton /* flush L2 cache */ 1554baa0ab6SPaul Burton cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); 156219c2db3SPaul Burton 157219c2db3SPaul Burton /* ensure cache ops complete before any further memory accesses */ 158219c2db3SPaul Burton sync(); 15930374f98SPaul Burton } 16030374f98SPaul Burton 16130374f98SPaul Burton void invalidate_dcache_range(ulong start_addr, ulong stop) 16230374f98SPaul Burton { 16330374f98SPaul Burton unsigned long lsize = dcache_line_size(); 1644baa0ab6SPaul Burton unsigned long slsize = scache_line_size(); 16530374f98SPaul Burton 166fbb0de08SMarek Vasut /* aend will be miscalculated when size is zero, so we return here */ 167fbb0de08SMarek Vasut if (start_addr == stop) 168fbb0de08SMarek Vasut return; 169fbb0de08SMarek Vasut 1704baa0ab6SPaul Burton /* invalidate L2 cache */ 1714baa0ab6SPaul Burton cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); 1724baa0ab6SPaul Burton 173a95800e8SPaul Burton cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); 174219c2db3SPaul Burton 175219c2db3SPaul Burton /* ensure cache ops complete before any further memory accesses */ 176219c2db3SPaul Burton sync(); 17730374f98SPaul Burton } 178*2f85c2beSDaniel Schwierzeck 179*2f85c2beSDaniel Schwierzeck int dcache_status(void) 180*2f85c2beSDaniel Schwierzeck { 181*2f85c2beSDaniel Schwierzeck unsigned int cca = read_c0_config() & CONF_CM_CMASK; 182*2f85c2beSDaniel Schwierzeck return cca != CONF_CM_UNCACHED; 183*2f85c2beSDaniel Schwierzeck } 184*2f85c2beSDaniel Schwierzeck 185*2f85c2beSDaniel Schwierzeck void dcache_enable(void) 186*2f85c2beSDaniel Schwierzeck { 187*2f85c2beSDaniel Schwierzeck puts("Not supported!\n"); 188*2f85c2beSDaniel Schwierzeck } 189*2f85c2beSDaniel Schwierzeck 190*2f85c2beSDaniel Schwierzeck void dcache_disable(void) 191*2f85c2beSDaniel Schwierzeck { 192*2f85c2beSDaniel Schwierzeck /* change CCA to uncached */ 193*2f85c2beSDaniel Schwierzeck change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); 194*2f85c2beSDaniel Schwierzeck 195*2f85c2beSDaniel Schwierzeck /* ensure the pipeline doesn't contain now-invalid instructions */ 196*2f85c2beSDaniel Schwierzeck instruction_hazard_barrier(); 197*2f85c2beSDaniel Schwierzeck } 198