1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_INSERT_BOOT_CONFIG 32 select MIPS_L1_CACHE_SHIFT_6 33 select MIPS_L2_CACHE 34 select OF_CONTROL 35 select OF_ISA_BUS 36 select ROM_EXCEPTION_VECTORS 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SUPPORTS_CPU_MIPS32_R6 41 select SUPPORTS_CPU_MIPS64_R1 42 select SUPPORTS_CPU_MIPS64_R2 43 select SUPPORTS_CPU_MIPS64_R6 44 select SUPPORTS_LITTLE_ENDIAN 45 select SWAP_IO_SPACE 46 imply CMD_DM 47 48config TARGET_VCT 49 bool "Support vct" 50 select ROM_EXCEPTION_VECTORS 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_CPU_MIPS32_R1 53 select SUPPORTS_CPU_MIPS32_R2 54 select SYS_MIPS_CACHE_INIT_RAM_LOAD 55 56config ARCH_ATH79 57 bool "Support QCA/Atheros ath79" 58 select DM 59 select OF_CONTROL 60 imply CMD_DM 61 62config ARCH_MSCC 63 bool "Support MSCC VCore-III" 64 select OF_CONTROL 65 select DM 66 67config ARCH_BMIPS 68 bool "Support BMIPS SoCs" 69 select CLK 70 select CPU 71 select DM 72 select OF_CONTROL 73 select RAM 74 select SYSRESET 75 imply CMD_DM 76 77config ARCH_MT7620 78 bool "Support MT7620/7688 SoCs" 79 imply CMD_DM 80 select DISPLAY_CPUINFO 81 select DM 82 imply DM_ETH 83 imply DM_GPIO 84 select DM_SERIAL 85 imply DM_SPI 86 imply DM_SPI_FLASH 87 select ARCH_MISC_INIT 88 select MIPS_TUNE_24KC 89 select OF_CONTROL 90 select ROM_EXCEPTION_VECTORS 91 select SUPPORTS_CPU_MIPS32_R1 92 select SUPPORTS_CPU_MIPS32_R2 93 select SUPPORTS_LITTLE_ENDIAN 94 select SYSRESET 95 96config MACH_PIC32 97 bool "Support Microchip PIC32" 98 select DM 99 select OF_CONTROL 100 imply CMD_DM 101 102config TARGET_BOSTON 103 bool "Support Boston" 104 select DM 105 select DM_SERIAL 106 select MIPS_CM 107 select MIPS_L1_CACHE_SHIFT_6 108 select MIPS_L2_CACHE 109 select OF_BOARD_SETUP 110 select OF_CONTROL 111 select ROM_EXCEPTION_VECTORS 112 select SUPPORTS_BIG_ENDIAN 113 select SUPPORTS_CPU_MIPS32_R1 114 select SUPPORTS_CPU_MIPS32_R2 115 select SUPPORTS_CPU_MIPS32_R6 116 select SUPPORTS_CPU_MIPS64_R1 117 select SUPPORTS_CPU_MIPS64_R2 118 select SUPPORTS_CPU_MIPS64_R6 119 select SUPPORTS_LITTLE_ENDIAN 120 imply CMD_DM 121 122config TARGET_XILFPGA 123 bool "Support Imagination Xilfpga" 124 select DM 125 select DM_ETH 126 select DM_GPIO 127 select DM_SERIAL 128 select MIPS_L1_CACHE_SHIFT_4 129 select OF_CONTROL 130 select ROM_EXCEPTION_VECTORS 131 select SUPPORTS_CPU_MIPS32_R1 132 select SUPPORTS_CPU_MIPS32_R2 133 select SUPPORTS_LITTLE_ENDIAN 134 imply CMD_DM 135 help 136 This supports IMGTEC MIPSfpga platform 137 138endchoice 139 140source "board/imgtec/boston/Kconfig" 141source "board/imgtec/malta/Kconfig" 142source "board/imgtec/xilfpga/Kconfig" 143source "board/micronas/vct/Kconfig" 144source "board/qemu-mips/Kconfig" 145source "arch/mips/mach-ath79/Kconfig" 146source "arch/mips/mach-mscc/Kconfig" 147source "arch/mips/mach-bmips/Kconfig" 148source "arch/mips/mach-pic32/Kconfig" 149source "arch/mips/mach-mt7620/Kconfig" 150 151if MIPS 152 153choice 154 prompt "Endianness selection" 155 help 156 Some MIPS boards can be configured for either little or big endian 157 byte order. These modes require different U-Boot images. In general there 158 is one preferred byteorder for a particular system but some systems are 159 just as commonly used in the one or the other endianness. 160 161config SYS_BIG_ENDIAN 162 bool "Big endian" 163 depends on SUPPORTS_BIG_ENDIAN 164 165config SYS_LITTLE_ENDIAN 166 bool "Little endian" 167 depends on SUPPORTS_LITTLE_ENDIAN 168 169endchoice 170 171choice 172 prompt "CPU selection" 173 default CPU_MIPS32_R2 174 175config CPU_MIPS32_R1 176 bool "MIPS32 Release 1" 177 depends on SUPPORTS_CPU_MIPS32_R1 178 select 32BIT 179 help 180 Choose this option to build an U-Boot for release 1 through 5 of the 181 MIPS32 architecture. 182 183config CPU_MIPS32_R2 184 bool "MIPS32 Release 2" 185 depends on SUPPORTS_CPU_MIPS32_R2 186 select 32BIT 187 help 188 Choose this option to build an U-Boot for release 2 through 5 of the 189 MIPS32 architecture. 190 191config CPU_MIPS32_R6 192 bool "MIPS32 Release 6" 193 depends on SUPPORTS_CPU_MIPS32_R6 194 select 32BIT 195 help 196 Choose this option to build an U-Boot for release 6 or later of the 197 MIPS32 architecture. 198 199config CPU_MIPS64_R1 200 bool "MIPS64 Release 1" 201 depends on SUPPORTS_CPU_MIPS64_R1 202 select 64BIT 203 help 204 Choose this option to build a kernel for release 1 through 5 of the 205 MIPS64 architecture. 206 207config CPU_MIPS64_R2 208 bool "MIPS64 Release 2" 209 depends on SUPPORTS_CPU_MIPS64_R2 210 select 64BIT 211 help 212 Choose this option to build a kernel for release 2 through 5 of the 213 MIPS64 architecture. 214 215config CPU_MIPS64_R6 216 bool "MIPS64 Release 6" 217 depends on SUPPORTS_CPU_MIPS64_R6 218 select 64BIT 219 help 220 Choose this option to build a kernel for release 6 or later of the 221 MIPS64 architecture. 222 223endchoice 224 225menu "General setup" 226 227config ROM_EXCEPTION_VECTORS 228 bool "Build U-Boot image with exception vectors" 229 help 230 Enable this to include exception vectors in the U-Boot image. This is 231 required if the U-Boot entry point is equal to the address of the 232 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 233 U-Boot booted from parallel NOR flash). 234 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 235 In that case the image size will be reduced by 0x500 bytes. 236 237config MIPS_CM_BASE 238 hex "MIPS CM GCR Base Address" 239 depends on MIPS_CM 240 default 0x16100000 if TARGET_BOSTON 241 default 0x1fbf8000 242 help 243 The physical base address at which to map the MIPS Coherence Manager 244 Global Configuration Registers (GCRs). This should be set such that 245 the GCRs occupy a region of the physical address space which is 246 otherwise unused, or at minimum that software doesn't need to access. 247 248config MIPS_CACHE_INDEX_BASE 249 hex "Index base address for cache initialisation" 250 default 0x80000000 if CPU_MIPS32 251 default 0xffffffff80000000 if CPU_MIPS64 252 help 253 This is the base address for a memory block, which is used for 254 initialising the cache lines. This is also the base address of a memory 255 block which is used for loading and filling cache lines when 256 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 257 Normally this is CKSEG0. If the MIPS system needs to move this block 258 to some SRAM or ScratchPad RAM, adapt this option accordingly. 259 260config MIPS_RELOCATION_TABLE_SIZE 261 hex "Relocation table size" 262 range 0x100 0x10000 263 default "0x8000" 264 ---help--- 265 A table of relocation data will be appended to the U-Boot binary 266 and parsed in relocate_code() to fix up all offsets in the relocated 267 U-Boot. 268 269 This option allows the amount of space reserved for the table to be 270 adjusted in a range from 256 up to 64k. The default is 32k and should 271 be ok in most cases. Reduce this value to shrink the size of U-Boot 272 binary. 273 274 The build will fail and a valid size suggested if this is too small. 275 276 If unsure, leave at the default value. 277 278endmenu 279 280menu "OS boot interface" 281 282config MIPS_BOOT_CMDLINE_LEGACY 283 bool "Hand over legacy command line to Linux kernel" 284 default y 285 help 286 Enable this option if you want U-Boot to hand over the Yamon-style 287 command line to the kernel. All bootargs will be prepared as argc/argv 288 compatible list. The argument count (argc) is stored in register $a0. 289 The address of the argument list (argv) is stored in register $a1. 290 291config MIPS_BOOT_ENV_LEGACY 292 bool "Hand over legacy environment to Linux kernel" 293 default y 294 help 295 Enable this option if you want U-Boot to hand over the Yamon-style 296 environment to the kernel. Information like memory size, initrd 297 address and size will be prepared as zero-terminated key/value list. 298 The address of the environment is stored in register $a2. 299 300config MIPS_BOOT_FDT 301 bool "Hand over a flattened device tree to Linux kernel" 302 default n 303 help 304 Enable this option if you want U-Boot to hand over a flattened 305 device tree to the kernel. According to UHI register $a0 will be set 306 to -2 and the FDT address is stored in $a1. 307 308endmenu 309 310config SUPPORTS_BIG_ENDIAN 311 bool 312 313config SUPPORTS_LITTLE_ENDIAN 314 bool 315 316config SUPPORTS_CPU_MIPS32_R1 317 bool 318 319config SUPPORTS_CPU_MIPS32_R2 320 bool 321 322config SUPPORTS_CPU_MIPS32_R6 323 bool 324 325config SUPPORTS_CPU_MIPS64_R1 326 bool 327 328config SUPPORTS_CPU_MIPS64_R2 329 bool 330 331config SUPPORTS_CPU_MIPS64_R6 332 bool 333 334config CPU_MIPS32 335 bool 336 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 337 338config CPU_MIPS64 339 bool 340 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 341 342config MIPS_TUNE_4KC 343 bool 344 345config MIPS_TUNE_14KC 346 bool 347 348config MIPS_TUNE_24KC 349 bool 350 351config MIPS_TUNE_34KC 352 bool 353 354config MIPS_TUNE_74KC 355 bool 356 357config 32BIT 358 bool 359 360config 64BIT 361 bool 362 363config SWAP_IO_SPACE 364 bool 365 366config SYS_MIPS_CACHE_INIT_RAM_LOAD 367 bool 368 369config MIPS_INIT_STACK_IN_SRAM 370 bool 371 default n 372 help 373 Select this if the initial stack frame could be setup in SRAM. 374 Normally the initial stack frame is set up in DRAM which is often 375 only available after lowlevel_init. With this option the initial 376 stack frame and the early C environment is set up before 377 lowlevel_init. Thus lowlevel_init does not need to be implemented 378 in assembler. 379 380config SYS_DCACHE_SIZE 381 int 382 default 0 383 help 384 The total size of the L1 Dcache, if known at compile time. 385 386config SYS_DCACHE_LINE_SIZE 387 int 388 default 0 389 help 390 The size of L1 Dcache lines, if known at compile time. 391 392config SYS_ICACHE_SIZE 393 int 394 default 0 395 help 396 The total size of the L1 ICache, if known at compile time. 397 398config SYS_ICACHE_LINE_SIZE 399 int 400 default 0 401 help 402 The size of L1 Icache lines, if known at compile time. 403 404config SYS_CACHE_SIZE_AUTO 405 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 406 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 407 help 408 Select this (or let it be auto-selected by not defining any cache 409 sizes) in order to allow U-Boot to automatically detect the sizes 410 of caches at runtime. This has a small cost in code size & runtime 411 so if you know the cache configuration for your system at compile 412 time it would be beneficial to configure it. 413 414config MIPS_L1_CACHE_SHIFT_4 415 bool 416 417config MIPS_L1_CACHE_SHIFT_5 418 bool 419 420config MIPS_L1_CACHE_SHIFT_6 421 bool 422 423config MIPS_L1_CACHE_SHIFT_7 424 bool 425 426config MIPS_L1_CACHE_SHIFT 427 int 428 default "7" if MIPS_L1_CACHE_SHIFT_7 429 default "6" if MIPS_L1_CACHE_SHIFT_6 430 default "5" if MIPS_L1_CACHE_SHIFT_5 431 default "4" if MIPS_L1_CACHE_SHIFT_4 432 default "5" 433 434config MIPS_L2_CACHE 435 bool 436 help 437 Select this if your system includes an L2 cache and you want U-Boot 438 to initialise & maintain it. 439 440config DYNAMIC_IO_PORT_BASE 441 bool 442 443config MIPS_CM 444 bool 445 help 446 Select this if your system contains a MIPS Coherence Manager and you 447 wish U-Boot to configure it or make use of it to retrieve system 448 information such as cache configuration. 449 450config MIPS_INSERT_BOOT_CONFIG 451 bool 452 default n 453 help 454 Enable this to insert some board-specific boot configuration in 455 the U-Boot binary at offset 0x10. 456 457config MIPS_BOOT_CONFIG_WORD0 458 hex 459 depends on MIPS_INSERT_BOOT_CONFIG 460 default 0x420 if TARGET_MALTA 461 default 0x0 462 help 463 Value which is inserted as boot config word 0. 464 465config MIPS_BOOT_CONFIG_WORD1 466 hex 467 depends on MIPS_INSERT_BOOT_CONFIG 468 default 0x0 469 help 470 Value which is inserted as boot config word 1. 471 472endif 473 474endmenu 475