1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 24config TARGET_MALTA 25 bool "Support malta" 26 select DM 27 select DM_SERIAL 28 select DYNAMIC_IO_PORT_BASE 29 select MIPS_CM 30 select MIPS_L2_CACHE 31 select OF_CONTROL 32 select OF_ISA_BUS 33 select SUPPORTS_BIG_ENDIAN 34 select SUPPORTS_LITTLE_ENDIAN 35 select SUPPORTS_CPU_MIPS32_R1 36 select SUPPORTS_CPU_MIPS32_R2 37 select SUPPORTS_CPU_MIPS32_R6 38 select SUPPORTS_CPU_MIPS64_R1 39 select SUPPORTS_CPU_MIPS64_R2 40 select SUPPORTS_CPU_MIPS64_R6 41 select SWAP_IO_SPACE 42 select MIPS_L1_CACHE_SHIFT_6 43 44config TARGET_VCT 45 bool "Support vct" 46 select SUPPORTS_BIG_ENDIAN 47 select SUPPORTS_CPU_MIPS32_R1 48 select SUPPORTS_CPU_MIPS32_R2 49 select SYS_MIPS_CACHE_INIT_RAM_LOAD 50 51config TARGET_DBAU1X00 52 bool "Support dbau1x00" 53 select SUPPORTS_BIG_ENDIAN 54 select SUPPORTS_LITTLE_ENDIAN 55 select SUPPORTS_CPU_MIPS32_R1 56 select SUPPORTS_CPU_MIPS32_R2 57 select SYS_MIPS_CACHE_INIT_RAM_LOAD 58 select MIPS_TUNE_4KC 59 60config TARGET_PB1X00 61 bool "Support pb1x00" 62 select SUPPORTS_LITTLE_ENDIAN 63 select SUPPORTS_CPU_MIPS32_R1 64 select SUPPORTS_CPU_MIPS32_R2 65 select SYS_MIPS_CACHE_INIT_RAM_LOAD 66 select MIPS_TUNE_4KC 67 68config ARCH_ATH79 69 bool "Support QCA/Atheros ath79" 70 select OF_CONTROL 71 select DM 72 73config MACH_PIC32 74 bool "Support Microchip PIC32" 75 select OF_CONTROL 76 select DM 77 78config TARGET_BOSTON 79 bool "Support Boston" 80 select DM 81 select DM_SERIAL 82 select OF_CONTROL 83 select MIPS_CM 84 select MIPS_L1_CACHE_SHIFT_6 85 select MIPS_L2_CACHE 86 select SUPPORTS_BIG_ENDIAN 87 select SUPPORTS_LITTLE_ENDIAN 88 select SUPPORTS_CPU_MIPS32_R1 89 select SUPPORTS_CPU_MIPS32_R2 90 select SUPPORTS_CPU_MIPS32_R6 91 select SUPPORTS_CPU_MIPS64_R1 92 select SUPPORTS_CPU_MIPS64_R2 93 select SUPPORTS_CPU_MIPS64_R6 94 95config TARGET_XILFPGA 96 bool "Support Imagination Xilfpga" 97 select OF_CONTROL 98 select DM 99 select DM_SERIAL 100 select DM_GPIO 101 select DM_ETH 102 select SUPPORTS_LITTLE_ENDIAN 103 select SUPPORTS_CPU_MIPS32_R1 104 select SUPPORTS_CPU_MIPS32_R2 105 select MIPS_L1_CACHE_SHIFT_4 106 help 107 This supports IMGTEC MIPSfpga platform 108 109endchoice 110 111source "board/dbau1x00/Kconfig" 112source "board/imgtec/boston/Kconfig" 113source "board/imgtec/malta/Kconfig" 114source "board/imgtec/xilfpga/Kconfig" 115source "board/micronas/vct/Kconfig" 116source "board/pb1x00/Kconfig" 117source "board/qemu-mips/Kconfig" 118source "arch/mips/mach-ath79/Kconfig" 119source "arch/mips/mach-pic32/Kconfig" 120 121if MIPS 122 123choice 124 prompt "Endianness selection" 125 help 126 Some MIPS boards can be configured for either little or big endian 127 byte order. These modes require different U-Boot images. In general there 128 is one preferred byteorder for a particular system but some systems are 129 just as commonly used in the one or the other endianness. 130 131config SYS_BIG_ENDIAN 132 bool "Big endian" 133 depends on SUPPORTS_BIG_ENDIAN 134 135config SYS_LITTLE_ENDIAN 136 bool "Little endian" 137 depends on SUPPORTS_LITTLE_ENDIAN 138 139endchoice 140 141choice 142 prompt "CPU selection" 143 default CPU_MIPS32_R2 144 145config CPU_MIPS32_R1 146 bool "MIPS32 Release 1" 147 depends on SUPPORTS_CPU_MIPS32_R1 148 select 32BIT 149 help 150 Choose this option to build an U-Boot for release 1 through 5 of the 151 MIPS32 architecture. 152 153config CPU_MIPS32_R2 154 bool "MIPS32 Release 2" 155 depends on SUPPORTS_CPU_MIPS32_R2 156 select 32BIT 157 help 158 Choose this option to build an U-Boot for release 2 through 5 of the 159 MIPS32 architecture. 160 161config CPU_MIPS32_R6 162 bool "MIPS32 Release 6" 163 depends on SUPPORTS_CPU_MIPS32_R6 164 select 32BIT 165 help 166 Choose this option to build an U-Boot for release 6 or later of the 167 MIPS32 architecture. 168 169config CPU_MIPS64_R1 170 bool "MIPS64 Release 1" 171 depends on SUPPORTS_CPU_MIPS64_R1 172 select 64BIT 173 help 174 Choose this option to build a kernel for release 1 through 5 of the 175 MIPS64 architecture. 176 177config CPU_MIPS64_R2 178 bool "MIPS64 Release 2" 179 depends on SUPPORTS_CPU_MIPS64_R2 180 select 64BIT 181 help 182 Choose this option to build a kernel for release 2 through 5 of the 183 MIPS64 architecture. 184 185config CPU_MIPS64_R6 186 bool "MIPS64 Release 6" 187 depends on SUPPORTS_CPU_MIPS64_R6 188 select 64BIT 189 help 190 Choose this option to build a kernel for release 6 or later of the 191 MIPS64 architecture. 192 193endchoice 194 195menu "OS boot interface" 196 197config MIPS_BOOT_CMDLINE_LEGACY 198 bool "Hand over legacy command line to Linux kernel" 199 default y 200 help 201 Enable this option if you want U-Boot to hand over the Yamon-style 202 command line to the kernel. All bootargs will be prepared as argc/argv 203 compatible list. The argument count (argc) is stored in register $a0. 204 The address of the argument list (argv) is stored in register $a1. 205 206config MIPS_BOOT_ENV_LEGACY 207 bool "Hand over legacy environment to Linux kernel" 208 default y 209 help 210 Enable this option if you want U-Boot to hand over the Yamon-style 211 environment to the kernel. Information like memory size, initrd 212 address and size will be prepared as zero-terminated key/value list. 213 The address of the environment is stored in register $a2. 214 215config MIPS_BOOT_FDT 216 bool "Hand over a flattened device tree to Linux kernel" 217 default n 218 help 219 Enable this option if you want U-Boot to hand over a flattened 220 device tree to the kernel. According to UHI register $a0 will be set 221 to -2 and the FDT address is stored in $a1. 222 223endmenu 224 225config SUPPORTS_BIG_ENDIAN 226 bool 227 228config SUPPORTS_LITTLE_ENDIAN 229 bool 230 231config SUPPORTS_CPU_MIPS32_R1 232 bool 233 234config SUPPORTS_CPU_MIPS32_R2 235 bool 236 237config SUPPORTS_CPU_MIPS32_R6 238 bool 239 240config SUPPORTS_CPU_MIPS64_R1 241 bool 242 243config SUPPORTS_CPU_MIPS64_R2 244 bool 245 246config SUPPORTS_CPU_MIPS64_R6 247 bool 248 249config CPU_MIPS32 250 bool 251 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 252 253config CPU_MIPS64 254 bool 255 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 256 257config MIPS_TUNE_4KC 258 bool 259 260config MIPS_TUNE_14KC 261 bool 262 263config MIPS_TUNE_24KC 264 bool 265 266config MIPS_TUNE_34KC 267 bool 268 269config MIPS_TUNE_74KC 270 bool 271 272config 32BIT 273 bool 274 275config 64BIT 276 bool 277 278config SWAP_IO_SPACE 279 bool 280 281config SYS_MIPS_CACHE_INIT_RAM_LOAD 282 bool 283 284config SYS_DCACHE_SIZE 285 int 286 default 0 287 help 288 The total size of the L1 Dcache, if known at compile time. 289 290config SYS_DCACHE_LINE_SIZE 291 int 292 default 0 293 help 294 The size of L1 Dcache lines, if known at compile time. 295 296config SYS_ICACHE_SIZE 297 int 298 default 0 299 help 300 The total size of the L1 ICache, if known at compile time. 301 302config SYS_ICACHE_LINE_SIZE 303 int 304 default 0 305 help 306 The size of L1 Icache lines, if known at compile time. 307 308config SYS_CACHE_SIZE_AUTO 309 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 310 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 311 help 312 Select this (or let it be auto-selected by not defining any cache 313 sizes) in order to allow U-Boot to automatically detect the sizes 314 of caches at runtime. This has a small cost in code size & runtime 315 so if you know the cache configuration for your system at compile 316 time it would be beneficial to configure it. 317 318config MIPS_L1_CACHE_SHIFT_4 319 bool 320 321config MIPS_L1_CACHE_SHIFT_5 322 bool 323 324config MIPS_L1_CACHE_SHIFT_6 325 bool 326 327config MIPS_L1_CACHE_SHIFT_7 328 bool 329 330config MIPS_L1_CACHE_SHIFT 331 int 332 default "7" if MIPS_L1_CACHE_SHIFT_7 333 default "6" if MIPS_L1_CACHE_SHIFT_6 334 default "5" if MIPS_L1_CACHE_SHIFT_5 335 default "4" if MIPS_L1_CACHE_SHIFT_4 336 default "5" 337 338config MIPS_L2_CACHE 339 bool 340 help 341 Select this if your system includes an L2 cache and you want U-Boot 342 to initialise & maintain it. 343 344config DYNAMIC_IO_PORT_BASE 345 bool 346 347config MIPS_CM 348 bool 349 help 350 Select this if your system contains a MIPS Coherence Manager and you 351 wish U-Boot to configure it or make use of it to retrieve system 352 information such as cache configuration. 353 354config MIPS_CM_BASE 355 hex 356 default 0x1fbf8000 357 help 358 The physical base address at which to map the MIPS Coherence Manager 359 Global Configuration Registers (GCRs). This should be set such that 360 the GCRs occupy a region of the physical address space which is 361 otherwise unused, or at minimum that software doesn't need to access. 362 363endif 364 365endmenu 366