1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select ROM_EXCEPTION_VECTORS 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L2_CACHE 32 select OF_CONTROL 33 select OF_ISA_BUS 34 select SUPPORTS_BIG_ENDIAN 35 select SUPPORTS_LITTLE_ENDIAN 36 select SUPPORTS_CPU_MIPS32_R1 37 select SUPPORTS_CPU_MIPS32_R2 38 select SUPPORTS_CPU_MIPS32_R6 39 select SUPPORTS_CPU_MIPS64_R1 40 select SUPPORTS_CPU_MIPS64_R2 41 select SUPPORTS_CPU_MIPS64_R6 42 select SWAP_IO_SPACE 43 select MIPS_L1_CACHE_SHIFT_6 44 select ROM_EXCEPTION_VECTORS 45 46config TARGET_VCT 47 bool "Support vct" 48 select SUPPORTS_BIG_ENDIAN 49 select SUPPORTS_CPU_MIPS32_R1 50 select SUPPORTS_CPU_MIPS32_R2 51 select SYS_MIPS_CACHE_INIT_RAM_LOAD 52 select ROM_EXCEPTION_VECTORS 53 54config TARGET_DBAU1X00 55 bool "Support dbau1x00" 56 select SUPPORTS_BIG_ENDIAN 57 select SUPPORTS_LITTLE_ENDIAN 58 select SUPPORTS_CPU_MIPS32_R1 59 select SUPPORTS_CPU_MIPS32_R2 60 select SYS_MIPS_CACHE_INIT_RAM_LOAD 61 select ROM_EXCEPTION_VECTORS 62 select MIPS_TUNE_4KC 63 64config TARGET_PB1X00 65 bool "Support pb1x00" 66 select SUPPORTS_LITTLE_ENDIAN 67 select SUPPORTS_CPU_MIPS32_R1 68 select SUPPORTS_CPU_MIPS32_R2 69 select SYS_MIPS_CACHE_INIT_RAM_LOAD 70 select ROM_EXCEPTION_VECTORS 71 select MIPS_TUNE_4KC 72 73config ARCH_ATH79 74 bool "Support QCA/Atheros ath79" 75 select OF_CONTROL 76 select DM 77 78config ARCH_BMIPS 79 bool "Support BMIPS SoCs" 80 select OF_CONTROL 81 select DM 82 select CLK 83 select CPU 84 select RAM 85 select SYSRESET 86 87config MACH_PIC32 88 bool "Support Microchip PIC32" 89 select OF_CONTROL 90 select DM 91 92config TARGET_BOSTON 93 bool "Support Boston" 94 select DM 95 select DM_SERIAL 96 select OF_CONTROL 97 select MIPS_CM 98 select MIPS_L1_CACHE_SHIFT_6 99 select MIPS_L2_CACHE 100 select SUPPORTS_BIG_ENDIAN 101 select SUPPORTS_LITTLE_ENDIAN 102 select SUPPORTS_CPU_MIPS32_R1 103 select SUPPORTS_CPU_MIPS32_R2 104 select SUPPORTS_CPU_MIPS32_R6 105 select SUPPORTS_CPU_MIPS64_R1 106 select SUPPORTS_CPU_MIPS64_R2 107 select SUPPORTS_CPU_MIPS64_R6 108 select ROM_EXCEPTION_VECTORS 109 110config TARGET_XILFPGA 111 bool "Support Imagination Xilfpga" 112 select OF_CONTROL 113 select DM 114 select DM_SERIAL 115 select DM_GPIO 116 select DM_ETH 117 select SUPPORTS_LITTLE_ENDIAN 118 select SUPPORTS_CPU_MIPS32_R1 119 select SUPPORTS_CPU_MIPS32_R2 120 select MIPS_L1_CACHE_SHIFT_4 121 select ROM_EXCEPTION_VECTORS 122 help 123 This supports IMGTEC MIPSfpga platform 124 125endchoice 126 127source "board/dbau1x00/Kconfig" 128source "board/imgtec/boston/Kconfig" 129source "board/imgtec/malta/Kconfig" 130source "board/imgtec/xilfpga/Kconfig" 131source "board/micronas/vct/Kconfig" 132source "board/pb1x00/Kconfig" 133source "board/qemu-mips/Kconfig" 134source "arch/mips/mach-ath79/Kconfig" 135source "arch/mips/mach-bmips/Kconfig" 136source "arch/mips/mach-pic32/Kconfig" 137 138if MIPS 139 140choice 141 prompt "Endianness selection" 142 help 143 Some MIPS boards can be configured for either little or big endian 144 byte order. These modes require different U-Boot images. In general there 145 is one preferred byteorder for a particular system but some systems are 146 just as commonly used in the one or the other endianness. 147 148config SYS_BIG_ENDIAN 149 bool "Big endian" 150 depends on SUPPORTS_BIG_ENDIAN 151 152config SYS_LITTLE_ENDIAN 153 bool "Little endian" 154 depends on SUPPORTS_LITTLE_ENDIAN 155 156endchoice 157 158choice 159 prompt "CPU selection" 160 default CPU_MIPS32_R2 161 162config CPU_MIPS32_R1 163 bool "MIPS32 Release 1" 164 depends on SUPPORTS_CPU_MIPS32_R1 165 select 32BIT 166 help 167 Choose this option to build an U-Boot for release 1 through 5 of the 168 MIPS32 architecture. 169 170config CPU_MIPS32_R2 171 bool "MIPS32 Release 2" 172 depends on SUPPORTS_CPU_MIPS32_R2 173 select 32BIT 174 help 175 Choose this option to build an U-Boot for release 2 through 5 of the 176 MIPS32 architecture. 177 178config CPU_MIPS32_R6 179 bool "MIPS32 Release 6" 180 depends on SUPPORTS_CPU_MIPS32_R6 181 select 32BIT 182 help 183 Choose this option to build an U-Boot for release 6 or later of the 184 MIPS32 architecture. 185 186config CPU_MIPS64_R1 187 bool "MIPS64 Release 1" 188 depends on SUPPORTS_CPU_MIPS64_R1 189 select 64BIT 190 help 191 Choose this option to build a kernel for release 1 through 5 of the 192 MIPS64 architecture. 193 194config CPU_MIPS64_R2 195 bool "MIPS64 Release 2" 196 depends on SUPPORTS_CPU_MIPS64_R2 197 select 64BIT 198 help 199 Choose this option to build a kernel for release 2 through 5 of the 200 MIPS64 architecture. 201 202config CPU_MIPS64_R6 203 bool "MIPS64 Release 6" 204 depends on SUPPORTS_CPU_MIPS64_R6 205 select 64BIT 206 help 207 Choose this option to build a kernel for release 6 or later of the 208 MIPS64 architecture. 209 210endchoice 211 212menu "General setup" 213 214config ROM_EXCEPTION_VECTORS 215 bool "Build U-Boot image with exception vectors" 216 help 217 Enable this to include exception vectors in the U-Boot image. This is 218 required if the U-Boot entry point is equal to the address of the 219 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 220 U-Boot booted from parallel NOR flash). 221 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 222 In that case the image size will be reduced by 0x500 bytes. 223 224endmenu 225 226menu "OS boot interface" 227 228config MIPS_BOOT_CMDLINE_LEGACY 229 bool "Hand over legacy command line to Linux kernel" 230 default y 231 help 232 Enable this option if you want U-Boot to hand over the Yamon-style 233 command line to the kernel. All bootargs will be prepared as argc/argv 234 compatible list. The argument count (argc) is stored in register $a0. 235 The address of the argument list (argv) is stored in register $a1. 236 237config MIPS_BOOT_ENV_LEGACY 238 bool "Hand over legacy environment to Linux kernel" 239 default y 240 help 241 Enable this option if you want U-Boot to hand over the Yamon-style 242 environment to the kernel. Information like memory size, initrd 243 address and size will be prepared as zero-terminated key/value list. 244 The address of the environment is stored in register $a2. 245 246config MIPS_BOOT_FDT 247 bool "Hand over a flattened device tree to Linux kernel" 248 default n 249 help 250 Enable this option if you want U-Boot to hand over a flattened 251 device tree to the kernel. According to UHI register $a0 will be set 252 to -2 and the FDT address is stored in $a1. 253 254endmenu 255 256config SUPPORTS_BIG_ENDIAN 257 bool 258 259config SUPPORTS_LITTLE_ENDIAN 260 bool 261 262config SUPPORTS_CPU_MIPS32_R1 263 bool 264 265config SUPPORTS_CPU_MIPS32_R2 266 bool 267 268config SUPPORTS_CPU_MIPS32_R6 269 bool 270 271config SUPPORTS_CPU_MIPS64_R1 272 bool 273 274config SUPPORTS_CPU_MIPS64_R2 275 bool 276 277config SUPPORTS_CPU_MIPS64_R6 278 bool 279 280config CPU_MIPS32 281 bool 282 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 283 284config CPU_MIPS64 285 bool 286 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 287 288config MIPS_TUNE_4KC 289 bool 290 291config MIPS_TUNE_14KC 292 bool 293 294config MIPS_TUNE_24KC 295 bool 296 297config MIPS_TUNE_34KC 298 bool 299 300config MIPS_TUNE_74KC 301 bool 302 303config 32BIT 304 bool 305 306config 64BIT 307 bool 308 309config SWAP_IO_SPACE 310 bool 311 312config SYS_MIPS_CACHE_INIT_RAM_LOAD 313 bool 314 315config MIPS_INIT_STACK_IN_SRAM 316 bool 317 default n 318 help 319 Select this if the initial stack frame could be setup in SRAM. 320 Normally the initial stack frame is set up in DRAM which is often 321 only available after lowlevel_init. With this option the initial 322 stack frame and the early C environment is set up before 323 lowlevel_init. Thus lowlevel_init does not need to be implemented 324 in assembler. 325 326config SYS_DCACHE_SIZE 327 int 328 default 0 329 help 330 The total size of the L1 Dcache, if known at compile time. 331 332config SYS_DCACHE_LINE_SIZE 333 int 334 default 0 335 help 336 The size of L1 Dcache lines, if known at compile time. 337 338config SYS_ICACHE_SIZE 339 int 340 default 0 341 help 342 The total size of the L1 ICache, if known at compile time. 343 344config SYS_ICACHE_LINE_SIZE 345 int 346 default 0 347 help 348 The size of L1 Icache lines, if known at compile time. 349 350config SYS_CACHE_SIZE_AUTO 351 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 352 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 353 help 354 Select this (or let it be auto-selected by not defining any cache 355 sizes) in order to allow U-Boot to automatically detect the sizes 356 of caches at runtime. This has a small cost in code size & runtime 357 so if you know the cache configuration for your system at compile 358 time it would be beneficial to configure it. 359 360config MIPS_L1_CACHE_SHIFT_4 361 bool 362 363config MIPS_L1_CACHE_SHIFT_5 364 bool 365 366config MIPS_L1_CACHE_SHIFT_6 367 bool 368 369config MIPS_L1_CACHE_SHIFT_7 370 bool 371 372config MIPS_L1_CACHE_SHIFT 373 int 374 default "7" if MIPS_L1_CACHE_SHIFT_7 375 default "6" if MIPS_L1_CACHE_SHIFT_6 376 default "5" if MIPS_L1_CACHE_SHIFT_5 377 default "4" if MIPS_L1_CACHE_SHIFT_4 378 default "5" 379 380config MIPS_L2_CACHE 381 bool 382 help 383 Select this if your system includes an L2 cache and you want U-Boot 384 to initialise & maintain it. 385 386config DYNAMIC_IO_PORT_BASE 387 bool 388 389config MIPS_CM 390 bool 391 help 392 Select this if your system contains a MIPS Coherence Manager and you 393 wish U-Boot to configure it or make use of it to retrieve system 394 information such as cache configuration. 395 396config MIPS_CM_BASE 397 hex 398 default 0x1fbf8000 399 help 400 The physical base address at which to map the MIPS Coherence Manager 401 Global Configuration Registers (GCRs). This should be set such that 402 the GCRs occupy a region of the physical address space which is 403 otherwise unused, or at minimum that software doesn't need to access. 404 405endif 406 407endmenu 408