1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 24config TARGET_MALTA 25 bool "Support malta" 26 select DYNAMIC_IO_PORT_BASE 27 select SUPPORTS_BIG_ENDIAN 28 select SUPPORTS_LITTLE_ENDIAN 29 select SUPPORTS_CPU_MIPS32_R1 30 select SUPPORTS_CPU_MIPS32_R2 31 select SUPPORTS_CPU_MIPS32_R6 32 select SWAP_IO_SPACE 33 select MIPS_L1_CACHE_SHIFT_6 34 35config TARGET_VCT 36 bool "Support vct" 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SYS_MIPS_CACHE_INIT_RAM_LOAD 41 42config TARGET_DBAU1X00 43 bool "Support dbau1x00" 44 select SUPPORTS_BIG_ENDIAN 45 select SUPPORTS_LITTLE_ENDIAN 46 select SUPPORTS_CPU_MIPS32_R1 47 select SUPPORTS_CPU_MIPS32_R2 48 select SYS_MIPS_CACHE_INIT_RAM_LOAD 49 select MIPS_TUNE_4KC 50 51config TARGET_PB1X00 52 bool "Support pb1x00" 53 select SUPPORTS_LITTLE_ENDIAN 54 select SUPPORTS_CPU_MIPS32_R1 55 select SUPPORTS_CPU_MIPS32_R2 56 select SYS_MIPS_CACHE_INIT_RAM_LOAD 57 select MIPS_TUNE_4KC 58 59config ARCH_ATH79 60 bool "Support QCA/Atheros ath79" 61 select OF_CONTROL 62 select DM 63 64config MACH_PIC32 65 bool "Support Microchip PIC32" 66 select OF_CONTROL 67 select DM 68 69endchoice 70 71source "board/dbau1x00/Kconfig" 72source "board/imgtec/malta/Kconfig" 73source "board/micronas/vct/Kconfig" 74source "board/pb1x00/Kconfig" 75source "board/qemu-mips/Kconfig" 76source "arch/mips/mach-ath79/Kconfig" 77source "arch/mips/mach-pic32/Kconfig" 78 79if MIPS 80 81choice 82 prompt "Endianness selection" 83 help 84 Some MIPS boards can be configured for either little or big endian 85 byte order. These modes require different U-Boot images. In general there 86 is one preferred byteorder for a particular system but some systems are 87 just as commonly used in the one or the other endianness. 88 89config SYS_BIG_ENDIAN 90 bool "Big endian" 91 depends on SUPPORTS_BIG_ENDIAN 92 93config SYS_LITTLE_ENDIAN 94 bool "Little endian" 95 depends on SUPPORTS_LITTLE_ENDIAN 96 97endchoice 98 99choice 100 prompt "CPU selection" 101 default CPU_MIPS32_R2 102 103config CPU_MIPS32_R1 104 bool "MIPS32 Release 1" 105 depends on SUPPORTS_CPU_MIPS32_R1 106 select 32BIT 107 help 108 Choose this option to build an U-Boot for release 1 through 5 of the 109 MIPS32 architecture. 110 111config CPU_MIPS32_R2 112 bool "MIPS32 Release 2" 113 depends on SUPPORTS_CPU_MIPS32_R2 114 select 32BIT 115 help 116 Choose this option to build an U-Boot for release 2 through 5 of the 117 MIPS32 architecture. 118 119config CPU_MIPS32_R6 120 bool "MIPS32 Release 6" 121 depends on SUPPORTS_CPU_MIPS32_R6 122 select 32BIT 123 help 124 Choose this option to build an U-Boot for release 6 or later of the 125 MIPS32 architecture. 126 127config CPU_MIPS64_R1 128 bool "MIPS64 Release 1" 129 depends on SUPPORTS_CPU_MIPS64_R1 130 select 64BIT 131 help 132 Choose this option to build a kernel for release 1 through 5 of the 133 MIPS64 architecture. 134 135config CPU_MIPS64_R2 136 bool "MIPS64 Release 2" 137 depends on SUPPORTS_CPU_MIPS64_R2 138 select 64BIT 139 help 140 Choose this option to build a kernel for release 2 through 5 of the 141 MIPS64 architecture. 142 143config CPU_MIPS64_R6 144 bool "MIPS64 Release 6" 145 depends on SUPPORTS_CPU_MIPS64_R6 146 select 64BIT 147 help 148 Choose this option to build a kernel for release 6 or later of the 149 MIPS64 architecture. 150 151endchoice 152 153menu "OS boot interface" 154 155config MIPS_BOOT_CMDLINE_LEGACY 156 bool "Hand over legacy command line to Linux kernel" 157 default y 158 help 159 Enable this option if you want U-Boot to hand over the Yamon-style 160 command line to the kernel. All bootargs will be prepared as argc/argv 161 compatible list. The argument count (argc) is stored in register $a0. 162 The address of the argument list (argv) is stored in register $a1. 163 164config MIPS_BOOT_ENV_LEGACY 165 bool "Hand over legacy environment to Linux kernel" 166 default y 167 help 168 Enable this option if you want U-Boot to hand over the Yamon-style 169 environment to the kernel. Information like memory size, initrd 170 address and size will be prepared as zero-terminated key/value list. 171 The address of the environment is stored in register $a2. 172 173config MIPS_BOOT_FDT 174 bool "Hand over a flattened device tree to Linux kernel" 175 default n 176 help 177 Enable this option if you want U-Boot to hand over a flattened 178 device tree to the kernel. According to UHI register $a0 will be set 179 to -2 and the FDT address is stored in $a1. 180 181endmenu 182 183config SUPPORTS_BIG_ENDIAN 184 bool 185 186config SUPPORTS_LITTLE_ENDIAN 187 bool 188 189config SUPPORTS_CPU_MIPS32_R1 190 bool 191 192config SUPPORTS_CPU_MIPS32_R2 193 bool 194 195config SUPPORTS_CPU_MIPS32_R6 196 bool 197 198config SUPPORTS_CPU_MIPS64_R1 199 bool 200 201config SUPPORTS_CPU_MIPS64_R2 202 bool 203 204config SUPPORTS_CPU_MIPS64_R6 205 bool 206 207config CPU_MIPS32 208 bool 209 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 210 211config CPU_MIPS64 212 bool 213 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 214 215config MIPS_TUNE_4KC 216 bool 217 218config MIPS_TUNE_14KC 219 bool 220 221config MIPS_TUNE_24KC 222 bool 223 224config MIPS_TUNE_74KC 225 bool 226 227config 32BIT 228 bool 229 230config 64BIT 231 bool 232 233config SWAP_IO_SPACE 234 bool 235 236config SYS_MIPS_CACHE_INIT_RAM_LOAD 237 bool 238 239config MIPS_L1_CACHE_SHIFT_4 240 bool 241 242config MIPS_L1_CACHE_SHIFT_5 243 bool 244 245config MIPS_L1_CACHE_SHIFT_6 246 bool 247 248config MIPS_L1_CACHE_SHIFT_7 249 bool 250 251config MIPS_L1_CACHE_SHIFT 252 int 253 default "7" if MIPS_L1_CACHE_SHIFT_7 254 default "6" if MIPS_L1_CACHE_SHIFT_6 255 default "5" if MIPS_L1_CACHE_SHIFT_5 256 default "4" if MIPS_L1_CACHE_SHIFT_4 257 default "5" 258 259config DYNAMIC_IO_PORT_BASE 260 bool 261 262endif 263 264endmenu 265