1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 24config TARGET_MALTA 25 bool "Support malta" 26 select DM 27 select DM_SERIAL 28 select DYNAMIC_IO_PORT_BASE 29 select MIPS_CM 30 select MIPS_L2_CACHE 31 select OF_CONTROL 32 select OF_ISA_BUS 33 select SUPPORTS_BIG_ENDIAN 34 select SUPPORTS_LITTLE_ENDIAN 35 select SUPPORTS_CPU_MIPS32_R1 36 select SUPPORTS_CPU_MIPS32_R2 37 select SUPPORTS_CPU_MIPS32_R6 38 select SUPPORTS_CPU_MIPS64_R1 39 select SUPPORTS_CPU_MIPS64_R2 40 select SUPPORTS_CPU_MIPS64_R6 41 select SWAP_IO_SPACE 42 select MIPS_L1_CACHE_SHIFT_6 43 44config TARGET_VCT 45 bool "Support vct" 46 select SUPPORTS_BIG_ENDIAN 47 select SUPPORTS_CPU_MIPS32_R1 48 select SUPPORTS_CPU_MIPS32_R2 49 select SYS_MIPS_CACHE_INIT_RAM_LOAD 50 51config TARGET_DBAU1X00 52 bool "Support dbau1x00" 53 select SUPPORTS_BIG_ENDIAN 54 select SUPPORTS_LITTLE_ENDIAN 55 select SUPPORTS_CPU_MIPS32_R1 56 select SUPPORTS_CPU_MIPS32_R2 57 select SYS_MIPS_CACHE_INIT_RAM_LOAD 58 select MIPS_TUNE_4KC 59 60config TARGET_PB1X00 61 bool "Support pb1x00" 62 select SUPPORTS_LITTLE_ENDIAN 63 select SUPPORTS_CPU_MIPS32_R1 64 select SUPPORTS_CPU_MIPS32_R2 65 select SYS_MIPS_CACHE_INIT_RAM_LOAD 66 select MIPS_TUNE_4KC 67 68config ARCH_ATH79 69 bool "Support QCA/Atheros ath79" 70 select OF_CONTROL 71 select DM 72 73config MACH_PIC32 74 bool "Support Microchip PIC32" 75 select OF_CONTROL 76 select DM 77 78config TARGET_XILFPGA 79 bool "Support Imagination Xilfpga" 80 select OF_CONTROL 81 select DM 82 select DM_SERIAL 83 select DM_GPIO 84 select DM_ETH 85 select SUPPORTS_LITTLE_ENDIAN 86 select SUPPORTS_CPU_MIPS32_R1 87 select SUPPORTS_CPU_MIPS32_R2 88 select MIPS_L1_CACHE_SHIFT_4 89 help 90 This supports IMGTEC MIPSfpga platform 91 92endchoice 93 94source "board/dbau1x00/Kconfig" 95source "board/imgtec/malta/Kconfig" 96source "board/imgtec/xilfpga/Kconfig" 97source "board/micronas/vct/Kconfig" 98source "board/pb1x00/Kconfig" 99source "board/qemu-mips/Kconfig" 100source "arch/mips/mach-ath79/Kconfig" 101source "arch/mips/mach-pic32/Kconfig" 102 103if MIPS 104 105choice 106 prompt "Endianness selection" 107 help 108 Some MIPS boards can be configured for either little or big endian 109 byte order. These modes require different U-Boot images. In general there 110 is one preferred byteorder for a particular system but some systems are 111 just as commonly used in the one or the other endianness. 112 113config SYS_BIG_ENDIAN 114 bool "Big endian" 115 depends on SUPPORTS_BIG_ENDIAN 116 117config SYS_LITTLE_ENDIAN 118 bool "Little endian" 119 depends on SUPPORTS_LITTLE_ENDIAN 120 121endchoice 122 123choice 124 prompt "CPU selection" 125 default CPU_MIPS32_R2 126 127config CPU_MIPS32_R1 128 bool "MIPS32 Release 1" 129 depends on SUPPORTS_CPU_MIPS32_R1 130 select 32BIT 131 help 132 Choose this option to build an U-Boot for release 1 through 5 of the 133 MIPS32 architecture. 134 135config CPU_MIPS32_R2 136 bool "MIPS32 Release 2" 137 depends on SUPPORTS_CPU_MIPS32_R2 138 select 32BIT 139 help 140 Choose this option to build an U-Boot for release 2 through 5 of the 141 MIPS32 architecture. 142 143config CPU_MIPS32_R6 144 bool "MIPS32 Release 6" 145 depends on SUPPORTS_CPU_MIPS32_R6 146 select 32BIT 147 help 148 Choose this option to build an U-Boot for release 6 or later of the 149 MIPS32 architecture. 150 151config CPU_MIPS64_R1 152 bool "MIPS64 Release 1" 153 depends on SUPPORTS_CPU_MIPS64_R1 154 select 64BIT 155 help 156 Choose this option to build a kernel for release 1 through 5 of the 157 MIPS64 architecture. 158 159config CPU_MIPS64_R2 160 bool "MIPS64 Release 2" 161 depends on SUPPORTS_CPU_MIPS64_R2 162 select 64BIT 163 help 164 Choose this option to build a kernel for release 2 through 5 of the 165 MIPS64 architecture. 166 167config CPU_MIPS64_R6 168 bool "MIPS64 Release 6" 169 depends on SUPPORTS_CPU_MIPS64_R6 170 select 64BIT 171 help 172 Choose this option to build a kernel for release 6 or later of the 173 MIPS64 architecture. 174 175endchoice 176 177menu "OS boot interface" 178 179config MIPS_BOOT_CMDLINE_LEGACY 180 bool "Hand over legacy command line to Linux kernel" 181 default y 182 help 183 Enable this option if you want U-Boot to hand over the Yamon-style 184 command line to the kernel. All bootargs will be prepared as argc/argv 185 compatible list. The argument count (argc) is stored in register $a0. 186 The address of the argument list (argv) is stored in register $a1. 187 188config MIPS_BOOT_ENV_LEGACY 189 bool "Hand over legacy environment to Linux kernel" 190 default y 191 help 192 Enable this option if you want U-Boot to hand over the Yamon-style 193 environment to the kernel. Information like memory size, initrd 194 address and size will be prepared as zero-terminated key/value list. 195 The address of the environment is stored in register $a2. 196 197config MIPS_BOOT_FDT 198 bool "Hand over a flattened device tree to Linux kernel" 199 default n 200 help 201 Enable this option if you want U-Boot to hand over a flattened 202 device tree to the kernel. According to UHI register $a0 will be set 203 to -2 and the FDT address is stored in $a1. 204 205endmenu 206 207config SUPPORTS_BIG_ENDIAN 208 bool 209 210config SUPPORTS_LITTLE_ENDIAN 211 bool 212 213config SUPPORTS_CPU_MIPS32_R1 214 bool 215 216config SUPPORTS_CPU_MIPS32_R2 217 bool 218 219config SUPPORTS_CPU_MIPS32_R6 220 bool 221 222config SUPPORTS_CPU_MIPS64_R1 223 bool 224 225config SUPPORTS_CPU_MIPS64_R2 226 bool 227 228config SUPPORTS_CPU_MIPS64_R6 229 bool 230 231config CPU_MIPS32 232 bool 233 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 234 235config CPU_MIPS64 236 bool 237 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 238 239config MIPS_TUNE_4KC 240 bool 241 242config MIPS_TUNE_14KC 243 bool 244 245config MIPS_TUNE_24KC 246 bool 247 248config MIPS_TUNE_34KC 249 bool 250 251config MIPS_TUNE_74KC 252 bool 253 254config 32BIT 255 bool 256 257config 64BIT 258 bool 259 260config SWAP_IO_SPACE 261 bool 262 263config SYS_MIPS_CACHE_INIT_RAM_LOAD 264 bool 265 266config SYS_DCACHE_SIZE 267 int 268 default 0 269 help 270 The total size of the L1 Dcache, if known at compile time. 271 272config SYS_DCACHE_LINE_SIZE 273 int 274 default 0 275 help 276 The size of L1 Dcache lines, if known at compile time. 277 278config SYS_ICACHE_SIZE 279 int 280 default 0 281 help 282 The total size of the L1 ICache, if known at compile time. 283 284config SYS_ICACHE_LINE_SIZE 285 int 286 default 0 287 help 288 The size of L1 Icache lines, if known at compile time. 289 290config SYS_CACHE_SIZE_AUTO 291 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 292 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 293 help 294 Select this (or let it be auto-selected by not defining any cache 295 sizes) in order to allow U-Boot to automatically detect the sizes 296 of caches at runtime. This has a small cost in code size & runtime 297 so if you know the cache configuration for your system at compile 298 time it would be beneficial to configure it. 299 300config MIPS_L1_CACHE_SHIFT_4 301 bool 302 303config MIPS_L1_CACHE_SHIFT_5 304 bool 305 306config MIPS_L1_CACHE_SHIFT_6 307 bool 308 309config MIPS_L1_CACHE_SHIFT_7 310 bool 311 312config MIPS_L1_CACHE_SHIFT 313 int 314 default "7" if MIPS_L1_CACHE_SHIFT_7 315 default "6" if MIPS_L1_CACHE_SHIFT_6 316 default "5" if MIPS_L1_CACHE_SHIFT_5 317 default "4" if MIPS_L1_CACHE_SHIFT_4 318 default "5" 319 320config MIPS_L2_CACHE 321 bool 322 help 323 Select this if your system includes an L2 cache and you want U-Boot 324 to initialise & maintain it. 325 326config DYNAMIC_IO_PORT_BASE 327 bool 328 329config MIPS_CM 330 bool 331 help 332 Select this if your system contains a MIPS Coherence Manager and you 333 wish U-Boot to configure it or make use of it to retrieve system 334 information such as cache configuration. 335 336config MIPS_CM_BASE 337 hex 338 default 0x1fbf8000 339 help 340 The physical base address at which to map the MIPS Coherence Manager 341 Global Configuration Registers (GCRs). This should be set such that 342 the GCRs occupy a region of the physical address space which is 343 otherwise unused, or at minimum that software doesn't need to access. 344 345endif 346 347endmenu 348