1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_INSERT_BOOT_CONFIG 32 select MIPS_L1_CACHE_SHIFT_6 33 select MIPS_L2_CACHE 34 select OF_CONTROL 35 select OF_ISA_BUS 36 select ROM_EXCEPTION_VECTORS 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SUPPORTS_CPU_MIPS32_R6 41 select SUPPORTS_CPU_MIPS64_R1 42 select SUPPORTS_CPU_MIPS64_R2 43 select SUPPORTS_CPU_MIPS64_R6 44 select SUPPORTS_LITTLE_ENDIAN 45 select SWAP_IO_SPACE 46 imply CMD_DM 47 48config TARGET_VCT 49 bool "Support vct" 50 select ROM_EXCEPTION_VECTORS 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_CPU_MIPS32_R1 53 select SUPPORTS_CPU_MIPS32_R2 54 select SYS_MIPS_CACHE_INIT_RAM_LOAD 55 56config ARCH_ATH79 57 bool "Support QCA/Atheros ath79" 58 select DM 59 select OF_CONTROL 60 imply CMD_DM 61 62config ARCH_BMIPS 63 bool "Support BMIPS SoCs" 64 select CLK 65 select CPU 66 select DM 67 select OF_CONTROL 68 select RAM 69 select SYSRESET 70 imply CMD_DM 71 72config ARCH_MT7620 73 bool "Support MT7620/7688 SoCs" 74 imply CMD_DM 75 select DISPLAY_CPUINFO 76 select DM 77 select DM_SERIAL 78 imply DM_SPI 79 imply DM_SPI_FLASH 80 select MIPS_TUNE_24KC 81 select OF_CONTROL 82 select ROM_EXCEPTION_VECTORS 83 select SUPPORTS_CPU_MIPS32_R1 84 select SUPPORTS_CPU_MIPS32_R2 85 select SUPPORTS_LITTLE_ENDIAN 86 87config MACH_PIC32 88 bool "Support Microchip PIC32" 89 select DM 90 select OF_CONTROL 91 imply CMD_DM 92 93config TARGET_BOSTON 94 bool "Support Boston" 95 select DM 96 select DM_SERIAL 97 select MIPS_CM 98 select MIPS_L1_CACHE_SHIFT_6 99 select MIPS_L2_CACHE 100 select OF_BOARD_SETUP 101 select OF_CONTROL 102 select ROM_EXCEPTION_VECTORS 103 select SUPPORTS_BIG_ENDIAN 104 select SUPPORTS_CPU_MIPS32_R1 105 select SUPPORTS_CPU_MIPS32_R2 106 select SUPPORTS_CPU_MIPS32_R6 107 select SUPPORTS_CPU_MIPS64_R1 108 select SUPPORTS_CPU_MIPS64_R2 109 select SUPPORTS_CPU_MIPS64_R6 110 select SUPPORTS_LITTLE_ENDIAN 111 imply CMD_DM 112 113config TARGET_XILFPGA 114 bool "Support Imagination Xilfpga" 115 select DM 116 select DM_ETH 117 select DM_GPIO 118 select DM_SERIAL 119 select MIPS_L1_CACHE_SHIFT_4 120 select OF_CONTROL 121 select ROM_EXCEPTION_VECTORS 122 select SUPPORTS_CPU_MIPS32_R1 123 select SUPPORTS_CPU_MIPS32_R2 124 select SUPPORTS_LITTLE_ENDIAN 125 imply CMD_DM 126 help 127 This supports IMGTEC MIPSfpga platform 128 129endchoice 130 131source "board/imgtec/boston/Kconfig" 132source "board/imgtec/malta/Kconfig" 133source "board/imgtec/xilfpga/Kconfig" 134source "board/micronas/vct/Kconfig" 135source "board/qemu-mips/Kconfig" 136source "arch/mips/mach-ath79/Kconfig" 137source "arch/mips/mach-bmips/Kconfig" 138source "arch/mips/mach-pic32/Kconfig" 139source "arch/mips/mach-mt7620/Kconfig" 140 141if MIPS 142 143choice 144 prompt "Endianness selection" 145 help 146 Some MIPS boards can be configured for either little or big endian 147 byte order. These modes require different U-Boot images. In general there 148 is one preferred byteorder for a particular system but some systems are 149 just as commonly used in the one or the other endianness. 150 151config SYS_BIG_ENDIAN 152 bool "Big endian" 153 depends on SUPPORTS_BIG_ENDIAN 154 155config SYS_LITTLE_ENDIAN 156 bool "Little endian" 157 depends on SUPPORTS_LITTLE_ENDIAN 158 159endchoice 160 161choice 162 prompt "CPU selection" 163 default CPU_MIPS32_R2 164 165config CPU_MIPS32_R1 166 bool "MIPS32 Release 1" 167 depends on SUPPORTS_CPU_MIPS32_R1 168 select 32BIT 169 help 170 Choose this option to build an U-Boot for release 1 through 5 of the 171 MIPS32 architecture. 172 173config CPU_MIPS32_R2 174 bool "MIPS32 Release 2" 175 depends on SUPPORTS_CPU_MIPS32_R2 176 select 32BIT 177 help 178 Choose this option to build an U-Boot for release 2 through 5 of the 179 MIPS32 architecture. 180 181config CPU_MIPS32_R6 182 bool "MIPS32 Release 6" 183 depends on SUPPORTS_CPU_MIPS32_R6 184 select 32BIT 185 help 186 Choose this option to build an U-Boot for release 6 or later of the 187 MIPS32 architecture. 188 189config CPU_MIPS64_R1 190 bool "MIPS64 Release 1" 191 depends on SUPPORTS_CPU_MIPS64_R1 192 select 64BIT 193 help 194 Choose this option to build a kernel for release 1 through 5 of the 195 MIPS64 architecture. 196 197config CPU_MIPS64_R2 198 bool "MIPS64 Release 2" 199 depends on SUPPORTS_CPU_MIPS64_R2 200 select 64BIT 201 help 202 Choose this option to build a kernel for release 2 through 5 of the 203 MIPS64 architecture. 204 205config CPU_MIPS64_R6 206 bool "MIPS64 Release 6" 207 depends on SUPPORTS_CPU_MIPS64_R6 208 select 64BIT 209 help 210 Choose this option to build a kernel for release 6 or later of the 211 MIPS64 architecture. 212 213endchoice 214 215menu "General setup" 216 217config ROM_EXCEPTION_VECTORS 218 bool "Build U-Boot image with exception vectors" 219 help 220 Enable this to include exception vectors in the U-Boot image. This is 221 required if the U-Boot entry point is equal to the address of the 222 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 223 U-Boot booted from parallel NOR flash). 224 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 225 In that case the image size will be reduced by 0x500 bytes. 226 227config MIPS_CM_BASE 228 hex "MIPS CM GCR Base Address" 229 depends on MIPS_CM 230 default 0x16100000 if TARGET_BOSTON 231 default 0x1fbf8000 232 help 233 The physical base address at which to map the MIPS Coherence Manager 234 Global Configuration Registers (GCRs). This should be set such that 235 the GCRs occupy a region of the physical address space which is 236 otherwise unused, or at minimum that software doesn't need to access. 237 238config MIPS_CACHE_INDEX_BASE 239 hex "Index base address for cache initialisation" 240 default 0x80000000 if CPU_MIPS32 241 default 0xffffffff80000000 if CPU_MIPS64 242 help 243 This is the base address for a memory block, which is used for 244 initialising the cache lines. This is also the base address of a memory 245 block which is used for loading and filling cache lines when 246 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 247 Normally this is CKSEG0. If the MIPS system needs to move this block 248 to some SRAM or ScratchPad RAM, adapt this option accordingly. 249 250endmenu 251 252menu "OS boot interface" 253 254config MIPS_BOOT_CMDLINE_LEGACY 255 bool "Hand over legacy command line to Linux kernel" 256 default y 257 help 258 Enable this option if you want U-Boot to hand over the Yamon-style 259 command line to the kernel. All bootargs will be prepared as argc/argv 260 compatible list. The argument count (argc) is stored in register $a0. 261 The address of the argument list (argv) is stored in register $a1. 262 263config MIPS_BOOT_ENV_LEGACY 264 bool "Hand over legacy environment to Linux kernel" 265 default y 266 help 267 Enable this option if you want U-Boot to hand over the Yamon-style 268 environment to the kernel. Information like memory size, initrd 269 address and size will be prepared as zero-terminated key/value list. 270 The address of the environment is stored in register $a2. 271 272config MIPS_BOOT_FDT 273 bool "Hand over a flattened device tree to Linux kernel" 274 default n 275 help 276 Enable this option if you want U-Boot to hand over a flattened 277 device tree to the kernel. According to UHI register $a0 will be set 278 to -2 and the FDT address is stored in $a1. 279 280endmenu 281 282config SUPPORTS_BIG_ENDIAN 283 bool 284 285config SUPPORTS_LITTLE_ENDIAN 286 bool 287 288config SUPPORTS_CPU_MIPS32_R1 289 bool 290 291config SUPPORTS_CPU_MIPS32_R2 292 bool 293 294config SUPPORTS_CPU_MIPS32_R6 295 bool 296 297config SUPPORTS_CPU_MIPS64_R1 298 bool 299 300config SUPPORTS_CPU_MIPS64_R2 301 bool 302 303config SUPPORTS_CPU_MIPS64_R6 304 bool 305 306config CPU_MIPS32 307 bool 308 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 309 310config CPU_MIPS64 311 bool 312 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 313 314config MIPS_TUNE_4KC 315 bool 316 317config MIPS_TUNE_14KC 318 bool 319 320config MIPS_TUNE_24KC 321 bool 322 323config MIPS_TUNE_34KC 324 bool 325 326config MIPS_TUNE_74KC 327 bool 328 329config 32BIT 330 bool 331 332config 64BIT 333 bool 334 335config SWAP_IO_SPACE 336 bool 337 338config SYS_MIPS_CACHE_INIT_RAM_LOAD 339 bool 340 341config MIPS_INIT_STACK_IN_SRAM 342 bool 343 default n 344 help 345 Select this if the initial stack frame could be setup in SRAM. 346 Normally the initial stack frame is set up in DRAM which is often 347 only available after lowlevel_init. With this option the initial 348 stack frame and the early C environment is set up before 349 lowlevel_init. Thus lowlevel_init does not need to be implemented 350 in assembler. 351 352config SYS_DCACHE_SIZE 353 int 354 default 0 355 help 356 The total size of the L1 Dcache, if known at compile time. 357 358config SYS_DCACHE_LINE_SIZE 359 int 360 default 0 361 help 362 The size of L1 Dcache lines, if known at compile time. 363 364config SYS_ICACHE_SIZE 365 int 366 default 0 367 help 368 The total size of the L1 ICache, if known at compile time. 369 370config SYS_ICACHE_LINE_SIZE 371 int 372 default 0 373 help 374 The size of L1 Icache lines, if known at compile time. 375 376config SYS_CACHE_SIZE_AUTO 377 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 378 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 379 help 380 Select this (or let it be auto-selected by not defining any cache 381 sizes) in order to allow U-Boot to automatically detect the sizes 382 of caches at runtime. This has a small cost in code size & runtime 383 so if you know the cache configuration for your system at compile 384 time it would be beneficial to configure it. 385 386config MIPS_L1_CACHE_SHIFT_4 387 bool 388 389config MIPS_L1_CACHE_SHIFT_5 390 bool 391 392config MIPS_L1_CACHE_SHIFT_6 393 bool 394 395config MIPS_L1_CACHE_SHIFT_7 396 bool 397 398config MIPS_L1_CACHE_SHIFT 399 int 400 default "7" if MIPS_L1_CACHE_SHIFT_7 401 default "6" if MIPS_L1_CACHE_SHIFT_6 402 default "5" if MIPS_L1_CACHE_SHIFT_5 403 default "4" if MIPS_L1_CACHE_SHIFT_4 404 default "5" 405 406config MIPS_L2_CACHE 407 bool 408 help 409 Select this if your system includes an L2 cache and you want U-Boot 410 to initialise & maintain it. 411 412config DYNAMIC_IO_PORT_BASE 413 bool 414 415config MIPS_CM 416 bool 417 help 418 Select this if your system contains a MIPS Coherence Manager and you 419 wish U-Boot to configure it or make use of it to retrieve system 420 information such as cache configuration. 421 422config MIPS_INSERT_BOOT_CONFIG 423 bool 424 default n 425 help 426 Enable this to insert some board-specific boot configuration in 427 the U-Boot binary at offset 0x10. 428 429config MIPS_BOOT_CONFIG_WORD0 430 hex 431 depends on MIPS_INSERT_BOOT_CONFIG 432 default 0x420 if TARGET_MALTA 433 default 0x0 434 help 435 Value which is inserted as boot config word 0. 436 437config MIPS_BOOT_CONFIG_WORD1 438 hex 439 depends on MIPS_INSERT_BOOT_CONFIG 440 default 0x0 441 help 442 Value which is inserted as boot config word 1. 443 444endif 445 446endmenu 447