1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select ROM_EXCEPTION_VECTORS 24 imply ENV_IS_IN_FLASH 25 26config TARGET_MALTA 27 bool "Support malta" 28 select DM 29 select DM_SERIAL 30 select DYNAMIC_IO_PORT_BASE 31 select MIPS_CM 32 select MIPS_L2_CACHE 33 select OF_CONTROL 34 select OF_ISA_BUS 35 select SUPPORTS_BIG_ENDIAN 36 select SUPPORTS_LITTLE_ENDIAN 37 select SUPPORTS_CPU_MIPS32_R1 38 select SUPPORTS_CPU_MIPS32_R2 39 select SUPPORTS_CPU_MIPS32_R6 40 select SUPPORTS_CPU_MIPS64_R1 41 select SUPPORTS_CPU_MIPS64_R2 42 select SUPPORTS_CPU_MIPS64_R6 43 select SWAP_IO_SPACE 44 select MIPS_L1_CACHE_SHIFT_6 45 select ROM_EXCEPTION_VECTORS 46 imply ENV_IS_IN_FLASH 47 48config TARGET_VCT 49 bool "Support vct" 50 select SUPPORTS_BIG_ENDIAN 51 select SUPPORTS_CPU_MIPS32_R1 52 select SUPPORTS_CPU_MIPS32_R2 53 select SYS_MIPS_CACHE_INIT_RAM_LOAD 54 select ROM_EXCEPTION_VECTORS 55 56config TARGET_DBAU1X00 57 bool "Support dbau1x00" 58 select SUPPORTS_BIG_ENDIAN 59 select SUPPORTS_LITTLE_ENDIAN 60 select SUPPORTS_CPU_MIPS32_R1 61 select SUPPORTS_CPU_MIPS32_R2 62 select SYS_MIPS_CACHE_INIT_RAM_LOAD 63 select ROM_EXCEPTION_VECTORS 64 select MIPS_TUNE_4KC 65 66config TARGET_PB1X00 67 bool "Support pb1x00" 68 select SUPPORTS_LITTLE_ENDIAN 69 select SUPPORTS_CPU_MIPS32_R1 70 select SUPPORTS_CPU_MIPS32_R2 71 select SYS_MIPS_CACHE_INIT_RAM_LOAD 72 select ROM_EXCEPTION_VECTORS 73 select MIPS_TUNE_4KC 74 75config ARCH_ATH79 76 bool "Support QCA/Atheros ath79" 77 select OF_CONTROL 78 select DM 79 80config ARCH_BMIPS 81 bool "Support BMIPS SoCs" 82 select OF_CONTROL 83 select DM 84 select CLK 85 select CPU 86 select RAM 87 select SYSRESET 88 imply ENV_IS_NOWHERE 89 90config MACH_PIC32 91 bool "Support Microchip PIC32" 92 select OF_CONTROL 93 select DM 94 95config TARGET_BOSTON 96 bool "Support Boston" 97 select DM 98 select DM_SERIAL 99 select OF_CONTROL 100 select MIPS_CM 101 select MIPS_L1_CACHE_SHIFT_6 102 select MIPS_L2_CACHE 103 select OF_BOARD_SETUP 104 select SUPPORTS_BIG_ENDIAN 105 select SUPPORTS_LITTLE_ENDIAN 106 select SUPPORTS_CPU_MIPS32_R1 107 select SUPPORTS_CPU_MIPS32_R2 108 select SUPPORTS_CPU_MIPS32_R6 109 select SUPPORTS_CPU_MIPS64_R1 110 select SUPPORTS_CPU_MIPS64_R2 111 select SUPPORTS_CPU_MIPS64_R6 112 select ROM_EXCEPTION_VECTORS 113 imply ENV_IS_IN_FLASH 114 115config TARGET_XILFPGA 116 bool "Support Imagination Xilfpga" 117 select OF_CONTROL 118 select DM 119 select DM_SERIAL 120 select DM_GPIO 121 select DM_ETH 122 select SUPPORTS_LITTLE_ENDIAN 123 select SUPPORTS_CPU_MIPS32_R1 124 select SUPPORTS_CPU_MIPS32_R2 125 select MIPS_L1_CACHE_SHIFT_4 126 select ROM_EXCEPTION_VECTORS 127 help 128 This supports IMGTEC MIPSfpga platform 129 130endchoice 131 132source "board/dbau1x00/Kconfig" 133source "board/imgtec/boston/Kconfig" 134source "board/imgtec/malta/Kconfig" 135source "board/imgtec/xilfpga/Kconfig" 136source "board/micronas/vct/Kconfig" 137source "board/pb1x00/Kconfig" 138source "board/qemu-mips/Kconfig" 139source "arch/mips/mach-ath79/Kconfig" 140source "arch/mips/mach-bmips/Kconfig" 141source "arch/mips/mach-pic32/Kconfig" 142 143if MIPS 144 145choice 146 prompt "Endianness selection" 147 help 148 Some MIPS boards can be configured for either little or big endian 149 byte order. These modes require different U-Boot images. In general there 150 is one preferred byteorder for a particular system but some systems are 151 just as commonly used in the one or the other endianness. 152 153config SYS_BIG_ENDIAN 154 bool "Big endian" 155 depends on SUPPORTS_BIG_ENDIAN 156 157config SYS_LITTLE_ENDIAN 158 bool "Little endian" 159 depends on SUPPORTS_LITTLE_ENDIAN 160 161endchoice 162 163choice 164 prompt "CPU selection" 165 default CPU_MIPS32_R2 166 167config CPU_MIPS32_R1 168 bool "MIPS32 Release 1" 169 depends on SUPPORTS_CPU_MIPS32_R1 170 select 32BIT 171 help 172 Choose this option to build an U-Boot for release 1 through 5 of the 173 MIPS32 architecture. 174 175config CPU_MIPS32_R2 176 bool "MIPS32 Release 2" 177 depends on SUPPORTS_CPU_MIPS32_R2 178 select 32BIT 179 help 180 Choose this option to build an U-Boot for release 2 through 5 of the 181 MIPS32 architecture. 182 183config CPU_MIPS32_R6 184 bool "MIPS32 Release 6" 185 depends on SUPPORTS_CPU_MIPS32_R6 186 select 32BIT 187 help 188 Choose this option to build an U-Boot for release 6 or later of the 189 MIPS32 architecture. 190 191config CPU_MIPS64_R1 192 bool "MIPS64 Release 1" 193 depends on SUPPORTS_CPU_MIPS64_R1 194 select 64BIT 195 help 196 Choose this option to build a kernel for release 1 through 5 of the 197 MIPS64 architecture. 198 199config CPU_MIPS64_R2 200 bool "MIPS64 Release 2" 201 depends on SUPPORTS_CPU_MIPS64_R2 202 select 64BIT 203 imply ENV_IS_IN_FLASH 204 help 205 Choose this option to build a kernel for release 2 through 5 of the 206 MIPS64 architecture. 207 208config CPU_MIPS64_R6 209 bool "MIPS64 Release 6" 210 depends on SUPPORTS_CPU_MIPS64_R6 211 select 64BIT 212 help 213 Choose this option to build a kernel for release 6 or later of the 214 MIPS64 architecture. 215 216endchoice 217 218menu "General setup" 219 220config ROM_EXCEPTION_VECTORS 221 bool "Build U-Boot image with exception vectors" 222 help 223 Enable this to include exception vectors in the U-Boot image. This is 224 required if the U-Boot entry point is equal to the address of the 225 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 226 U-Boot booted from parallel NOR flash). 227 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 228 In that case the image size will be reduced by 0x500 bytes. 229 230config MIPS_CM_BASE 231 hex "MIPS CM GCR Base Address" 232 depends on MIPS_CM 233 default 0x16100000 if TARGET_BOSTON 234 default 0x1fbf8000 235 help 236 The physical base address at which to map the MIPS Coherence Manager 237 Global Configuration Registers (GCRs). This should be set such that 238 the GCRs occupy a region of the physical address space which is 239 otherwise unused, or at minimum that software doesn't need to access. 240 241endmenu 242 243menu "OS boot interface" 244 245config MIPS_BOOT_CMDLINE_LEGACY 246 bool "Hand over legacy command line to Linux kernel" 247 default y 248 help 249 Enable this option if you want U-Boot to hand over the Yamon-style 250 command line to the kernel. All bootargs will be prepared as argc/argv 251 compatible list. The argument count (argc) is stored in register $a0. 252 The address of the argument list (argv) is stored in register $a1. 253 254config MIPS_BOOT_ENV_LEGACY 255 bool "Hand over legacy environment to Linux kernel" 256 default y 257 help 258 Enable this option if you want U-Boot to hand over the Yamon-style 259 environment to the kernel. Information like memory size, initrd 260 address and size will be prepared as zero-terminated key/value list. 261 The address of the environment is stored in register $a2. 262 263config MIPS_BOOT_FDT 264 bool "Hand over a flattened device tree to Linux kernel" 265 default n 266 help 267 Enable this option if you want U-Boot to hand over a flattened 268 device tree to the kernel. According to UHI register $a0 will be set 269 to -2 and the FDT address is stored in $a1. 270 271endmenu 272 273config SUPPORTS_BIG_ENDIAN 274 bool 275 276config SUPPORTS_LITTLE_ENDIAN 277 bool 278 279config SUPPORTS_CPU_MIPS32_R1 280 bool 281 282config SUPPORTS_CPU_MIPS32_R2 283 bool 284 285config SUPPORTS_CPU_MIPS32_R6 286 bool 287 288config SUPPORTS_CPU_MIPS64_R1 289 bool 290 291config SUPPORTS_CPU_MIPS64_R2 292 bool 293 294config SUPPORTS_CPU_MIPS64_R6 295 bool 296 297config CPU_MIPS32 298 bool 299 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 300 301config CPU_MIPS64 302 bool 303 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 304 305config MIPS_TUNE_4KC 306 bool 307 308config MIPS_TUNE_14KC 309 bool 310 311config MIPS_TUNE_24KC 312 bool 313 314config MIPS_TUNE_34KC 315 bool 316 317config MIPS_TUNE_74KC 318 bool 319 320config 32BIT 321 bool 322 323config 64BIT 324 bool 325 326config SWAP_IO_SPACE 327 bool 328 329config SYS_MIPS_CACHE_INIT_RAM_LOAD 330 bool 331 332config MIPS_INIT_STACK_IN_SRAM 333 bool 334 default n 335 help 336 Select this if the initial stack frame could be setup in SRAM. 337 Normally the initial stack frame is set up in DRAM which is often 338 only available after lowlevel_init. With this option the initial 339 stack frame and the early C environment is set up before 340 lowlevel_init. Thus lowlevel_init does not need to be implemented 341 in assembler. 342 343config SYS_DCACHE_SIZE 344 int 345 default 0 346 help 347 The total size of the L1 Dcache, if known at compile time. 348 349config SYS_DCACHE_LINE_SIZE 350 int 351 default 0 352 help 353 The size of L1 Dcache lines, if known at compile time. 354 355config SYS_ICACHE_SIZE 356 int 357 default 0 358 help 359 The total size of the L1 ICache, if known at compile time. 360 361config SYS_ICACHE_LINE_SIZE 362 int 363 default 0 364 help 365 The size of L1 Icache lines, if known at compile time. 366 367config SYS_CACHE_SIZE_AUTO 368 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 369 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 370 help 371 Select this (or let it be auto-selected by not defining any cache 372 sizes) in order to allow U-Boot to automatically detect the sizes 373 of caches at runtime. This has a small cost in code size & runtime 374 so if you know the cache configuration for your system at compile 375 time it would be beneficial to configure it. 376 377config MIPS_L1_CACHE_SHIFT_4 378 bool 379 380config MIPS_L1_CACHE_SHIFT_5 381 bool 382 383config MIPS_L1_CACHE_SHIFT_6 384 bool 385 386config MIPS_L1_CACHE_SHIFT_7 387 bool 388 389config MIPS_L1_CACHE_SHIFT 390 int 391 default "7" if MIPS_L1_CACHE_SHIFT_7 392 default "6" if MIPS_L1_CACHE_SHIFT_6 393 default "5" if MIPS_L1_CACHE_SHIFT_5 394 default "4" if MIPS_L1_CACHE_SHIFT_4 395 default "5" 396 397config MIPS_L2_CACHE 398 bool 399 help 400 Select this if your system includes an L2 cache and you want U-Boot 401 to initialise & maintain it. 402 403config DYNAMIC_IO_PORT_BASE 404 bool 405 406config MIPS_CM 407 bool 408 help 409 Select this if your system contains a MIPS Coherence Manager and you 410 wish U-Boot to configure it or make use of it to retrieve system 411 information such as cache configuration. 412 413endif 414 415endmenu 416