1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select ROM_EXCEPTION_VECTORS 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L2_CACHE 32 select OF_CONTROL 33 select OF_ISA_BUS 34 select SUPPORTS_BIG_ENDIAN 35 select SUPPORTS_LITTLE_ENDIAN 36 select SUPPORTS_CPU_MIPS32_R1 37 select SUPPORTS_CPU_MIPS32_R2 38 select SUPPORTS_CPU_MIPS32_R6 39 select SUPPORTS_CPU_MIPS64_R1 40 select SUPPORTS_CPU_MIPS64_R2 41 select SUPPORTS_CPU_MIPS64_R6 42 select SWAP_IO_SPACE 43 select MIPS_L1_CACHE_SHIFT_6 44 select ROM_EXCEPTION_VECTORS 45 46config TARGET_VCT 47 bool "Support vct" 48 select SUPPORTS_BIG_ENDIAN 49 select SUPPORTS_CPU_MIPS32_R1 50 select SUPPORTS_CPU_MIPS32_R2 51 select SYS_MIPS_CACHE_INIT_RAM_LOAD 52 select ROM_EXCEPTION_VECTORS 53 54config TARGET_DBAU1X00 55 bool "Support dbau1x00" 56 select SUPPORTS_BIG_ENDIAN 57 select SUPPORTS_LITTLE_ENDIAN 58 select SUPPORTS_CPU_MIPS32_R1 59 select SUPPORTS_CPU_MIPS32_R2 60 select SYS_MIPS_CACHE_INIT_RAM_LOAD 61 select ROM_EXCEPTION_VECTORS 62 select MIPS_TUNE_4KC 63 64config TARGET_PB1X00 65 bool "Support pb1x00" 66 select SUPPORTS_LITTLE_ENDIAN 67 select SUPPORTS_CPU_MIPS32_R1 68 select SUPPORTS_CPU_MIPS32_R2 69 select SYS_MIPS_CACHE_INIT_RAM_LOAD 70 select ROM_EXCEPTION_VECTORS 71 select MIPS_TUNE_4KC 72 73config ARCH_ATH79 74 bool "Support QCA/Atheros ath79" 75 select OF_CONTROL 76 select DM 77 78config MACH_PIC32 79 bool "Support Microchip PIC32" 80 select OF_CONTROL 81 select DM 82 83config TARGET_BOSTON 84 bool "Support Boston" 85 select DM 86 select DM_SERIAL 87 select OF_CONTROL 88 select MIPS_CM 89 select MIPS_L1_CACHE_SHIFT_6 90 select MIPS_L2_CACHE 91 select SUPPORTS_BIG_ENDIAN 92 select SUPPORTS_LITTLE_ENDIAN 93 select SUPPORTS_CPU_MIPS32_R1 94 select SUPPORTS_CPU_MIPS32_R2 95 select SUPPORTS_CPU_MIPS32_R6 96 select SUPPORTS_CPU_MIPS64_R1 97 select SUPPORTS_CPU_MIPS64_R2 98 select SUPPORTS_CPU_MIPS64_R6 99 select ROM_EXCEPTION_VECTORS 100 101config TARGET_XILFPGA 102 bool "Support Imagination Xilfpga" 103 select OF_CONTROL 104 select DM 105 select DM_SERIAL 106 select DM_GPIO 107 select DM_ETH 108 select SUPPORTS_LITTLE_ENDIAN 109 select SUPPORTS_CPU_MIPS32_R1 110 select SUPPORTS_CPU_MIPS32_R2 111 select MIPS_L1_CACHE_SHIFT_4 112 select ROM_EXCEPTION_VECTORS 113 help 114 This supports IMGTEC MIPSfpga platform 115 116endchoice 117 118source "board/dbau1x00/Kconfig" 119source "board/imgtec/boston/Kconfig" 120source "board/imgtec/malta/Kconfig" 121source "board/imgtec/xilfpga/Kconfig" 122source "board/micronas/vct/Kconfig" 123source "board/pb1x00/Kconfig" 124source "board/qemu-mips/Kconfig" 125source "arch/mips/mach-ath79/Kconfig" 126source "arch/mips/mach-pic32/Kconfig" 127 128if MIPS 129 130choice 131 prompt "Endianness selection" 132 help 133 Some MIPS boards can be configured for either little or big endian 134 byte order. These modes require different U-Boot images. In general there 135 is one preferred byteorder for a particular system but some systems are 136 just as commonly used in the one or the other endianness. 137 138config SYS_BIG_ENDIAN 139 bool "Big endian" 140 depends on SUPPORTS_BIG_ENDIAN 141 142config SYS_LITTLE_ENDIAN 143 bool "Little endian" 144 depends on SUPPORTS_LITTLE_ENDIAN 145 146endchoice 147 148choice 149 prompt "CPU selection" 150 default CPU_MIPS32_R2 151 152config CPU_MIPS32_R1 153 bool "MIPS32 Release 1" 154 depends on SUPPORTS_CPU_MIPS32_R1 155 select 32BIT 156 help 157 Choose this option to build an U-Boot for release 1 through 5 of the 158 MIPS32 architecture. 159 160config CPU_MIPS32_R2 161 bool "MIPS32 Release 2" 162 depends on SUPPORTS_CPU_MIPS32_R2 163 select 32BIT 164 help 165 Choose this option to build an U-Boot for release 2 through 5 of the 166 MIPS32 architecture. 167 168config CPU_MIPS32_R6 169 bool "MIPS32 Release 6" 170 depends on SUPPORTS_CPU_MIPS32_R6 171 select 32BIT 172 help 173 Choose this option to build an U-Boot for release 6 or later of the 174 MIPS32 architecture. 175 176config CPU_MIPS64_R1 177 bool "MIPS64 Release 1" 178 depends on SUPPORTS_CPU_MIPS64_R1 179 select 64BIT 180 help 181 Choose this option to build a kernel for release 1 through 5 of the 182 MIPS64 architecture. 183 184config CPU_MIPS64_R2 185 bool "MIPS64 Release 2" 186 depends on SUPPORTS_CPU_MIPS64_R2 187 select 64BIT 188 help 189 Choose this option to build a kernel for release 2 through 5 of the 190 MIPS64 architecture. 191 192config CPU_MIPS64_R6 193 bool "MIPS64 Release 6" 194 depends on SUPPORTS_CPU_MIPS64_R6 195 select 64BIT 196 help 197 Choose this option to build a kernel for release 6 or later of the 198 MIPS64 architecture. 199 200endchoice 201 202menu "General setup" 203 204config ROM_EXCEPTION_VECTORS 205 bool "Build U-Boot image with exception vectors" 206 help 207 Enable this to include exception vectors in the U-Boot image. This is 208 required if the U-Boot entry point is equal to the address of the 209 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 210 U-Boot booted from parallel NOR flash). 211 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 212 In that case the image size will be reduced by 0x500 bytes. 213 214endmenu 215 216menu "OS boot interface" 217 218config MIPS_BOOT_CMDLINE_LEGACY 219 bool "Hand over legacy command line to Linux kernel" 220 default y 221 help 222 Enable this option if you want U-Boot to hand over the Yamon-style 223 command line to the kernel. All bootargs will be prepared as argc/argv 224 compatible list. The argument count (argc) is stored in register $a0. 225 The address of the argument list (argv) is stored in register $a1. 226 227config MIPS_BOOT_ENV_LEGACY 228 bool "Hand over legacy environment to Linux kernel" 229 default y 230 help 231 Enable this option if you want U-Boot to hand over the Yamon-style 232 environment to the kernel. Information like memory size, initrd 233 address and size will be prepared as zero-terminated key/value list. 234 The address of the environment is stored in register $a2. 235 236config MIPS_BOOT_FDT 237 bool "Hand over a flattened device tree to Linux kernel" 238 default n 239 help 240 Enable this option if you want U-Boot to hand over a flattened 241 device tree to the kernel. According to UHI register $a0 will be set 242 to -2 and the FDT address is stored in $a1. 243 244endmenu 245 246config SUPPORTS_BIG_ENDIAN 247 bool 248 249config SUPPORTS_LITTLE_ENDIAN 250 bool 251 252config SUPPORTS_CPU_MIPS32_R1 253 bool 254 255config SUPPORTS_CPU_MIPS32_R2 256 bool 257 258config SUPPORTS_CPU_MIPS32_R6 259 bool 260 261config SUPPORTS_CPU_MIPS64_R1 262 bool 263 264config SUPPORTS_CPU_MIPS64_R2 265 bool 266 267config SUPPORTS_CPU_MIPS64_R6 268 bool 269 270config CPU_MIPS32 271 bool 272 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 273 274config CPU_MIPS64 275 bool 276 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 277 278config MIPS_TUNE_4KC 279 bool 280 281config MIPS_TUNE_14KC 282 bool 283 284config MIPS_TUNE_24KC 285 bool 286 287config MIPS_TUNE_34KC 288 bool 289 290config MIPS_TUNE_74KC 291 bool 292 293config 32BIT 294 bool 295 296config 64BIT 297 bool 298 299config SWAP_IO_SPACE 300 bool 301 302config SYS_MIPS_CACHE_INIT_RAM_LOAD 303 bool 304 305config MIPS_INIT_STACK_IN_SRAM 306 bool 307 default n 308 help 309 Select this if the initial stack frame could be setup in SRAM. 310 Normally the initial stack frame is set up in DRAM which is often 311 only available after lowlevel_init. With this option the initial 312 stack frame and the early C environment is set up before 313 lowlevel_init. Thus lowlevel_init does not need to be implemented 314 in assembler. 315 316config SYS_DCACHE_SIZE 317 int 318 default 0 319 help 320 The total size of the L1 Dcache, if known at compile time. 321 322config SYS_DCACHE_LINE_SIZE 323 int 324 default 0 325 help 326 The size of L1 Dcache lines, if known at compile time. 327 328config SYS_ICACHE_SIZE 329 int 330 default 0 331 help 332 The total size of the L1 ICache, if known at compile time. 333 334config SYS_ICACHE_LINE_SIZE 335 int 336 default 0 337 help 338 The size of L1 Icache lines, if known at compile time. 339 340config SYS_CACHE_SIZE_AUTO 341 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 342 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 343 help 344 Select this (or let it be auto-selected by not defining any cache 345 sizes) in order to allow U-Boot to automatically detect the sizes 346 of caches at runtime. This has a small cost in code size & runtime 347 so if you know the cache configuration for your system at compile 348 time it would be beneficial to configure it. 349 350config MIPS_L1_CACHE_SHIFT_4 351 bool 352 353config MIPS_L1_CACHE_SHIFT_5 354 bool 355 356config MIPS_L1_CACHE_SHIFT_6 357 bool 358 359config MIPS_L1_CACHE_SHIFT_7 360 bool 361 362config MIPS_L1_CACHE_SHIFT 363 int 364 default "7" if MIPS_L1_CACHE_SHIFT_7 365 default "6" if MIPS_L1_CACHE_SHIFT_6 366 default "5" if MIPS_L1_CACHE_SHIFT_5 367 default "4" if MIPS_L1_CACHE_SHIFT_4 368 default "5" 369 370config MIPS_L2_CACHE 371 bool 372 help 373 Select this if your system includes an L2 cache and you want U-Boot 374 to initialise & maintain it. 375 376config DYNAMIC_IO_PORT_BASE 377 bool 378 379config MIPS_CM 380 bool 381 help 382 Select this if your system contains a MIPS Coherence Manager and you 383 wish U-Boot to configure it or make use of it to retrieve system 384 information such as cache configuration. 385 386config MIPS_CM_BASE 387 hex 388 default 0x1fbf8000 389 help 390 The physical base address at which to map the MIPS Coherence Manager 391 Global Configuration Registers (GCRs). This should be set such that 392 the GCRs occupy a region of the physical address space which is 393 otherwise unused, or at minimum that software doesn't need to access. 394 395endif 396 397endmenu 398