1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2 9 default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2 10 11config USE_PRIVATE_LIBGCC 12 default y 13 14choice 15 prompt "Target select" 16 optional 17 18config TARGET_QEMU_MIPS 19 bool "Support qemu-mips" 20 select SUPPORTS_BIG_ENDIAN 21 select SUPPORTS_LITTLE_ENDIAN 22 select SUPPORTS_CPU_MIPS32_R1 23 select SUPPORTS_CPU_MIPS32_R2 24 select SUPPORTS_CPU_MIPS64_R1 25 select SUPPORTS_CPU_MIPS64_R2 26 27config TARGET_MALTA 28 bool "Support malta" 29 select SUPPORTS_BIG_ENDIAN 30 select SUPPORTS_LITTLE_ENDIAN 31 select SUPPORTS_CPU_MIPS32_R1 32 select SUPPORTS_CPU_MIPS32_R2 33 select SWAP_IO_SPACE 34 35config TARGET_VCT 36 bool "Support vct" 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SYS_MIPS_CACHE_INIT_RAM_LOAD 41 42config TARGET_DBAU1X00 43 bool "Support dbau1x00" 44 select SUPPORTS_BIG_ENDIAN 45 select SUPPORTS_LITTLE_ENDIAN 46 select SUPPORTS_CPU_MIPS32_R1 47 select SUPPORTS_CPU_MIPS32_R2 48 select SYS_MIPS_CACHE_INIT_RAM_LOAD 49 50config TARGET_PB1X00 51 bool "Support pb1x00" 52 select SUPPORTS_LITTLE_ENDIAN 53 select SUPPORTS_CPU_MIPS32_R1 54 select SUPPORTS_CPU_MIPS32_R2 55 select SYS_MIPS_CACHE_INIT_RAM_LOAD 56 57 58endchoice 59 60source "board/dbau1x00/Kconfig" 61source "board/imgtec/malta/Kconfig" 62source "board/micronas/vct/Kconfig" 63source "board/pb1x00/Kconfig" 64source "board/qemu-mips/Kconfig" 65 66if MIPS 67 68choice 69 prompt "Endianness selection" 70 help 71 Some MIPS boards can be configured for either little or big endian 72 byte order. These modes require different U-Boot images. In general there 73 is one preferred byteorder for a particular system but some systems are 74 just as commonly used in the one or the other endianness. 75 76config SYS_BIG_ENDIAN 77 bool "Big endian" 78 depends on SUPPORTS_BIG_ENDIAN 79 80config SYS_LITTLE_ENDIAN 81 bool "Little endian" 82 depends on SUPPORTS_LITTLE_ENDIAN 83 84endchoice 85 86choice 87 prompt "CPU selection" 88 default CPU_MIPS32_R2 89 90config CPU_MIPS32_R1 91 bool "MIPS32 Release 1" 92 depends on SUPPORTS_CPU_MIPS32_R1 93 select 32BIT 94 help 95 Choose this option to build an U-Boot for release 1 or later of the 96 MIPS32 architecture. 97 98config CPU_MIPS32_R2 99 bool "MIPS32 Release 2" 100 depends on SUPPORTS_CPU_MIPS32_R2 101 select 32BIT 102 help 103 Choose this option to build an U-Boot for release 2 or later of the 104 MIPS32 architecture. 105 106config CPU_MIPS64_R1 107 bool "MIPS64 Release 1" 108 depends on SUPPORTS_CPU_MIPS64_R1 109 select 64BIT 110 help 111 Choose this option to build a kernel for release 1 or later of the 112 MIPS64 architecture. 113 114config CPU_MIPS64_R2 115 bool "MIPS64 Release 2" 116 depends on SUPPORTS_CPU_MIPS64_R2 117 select 64BIT 118 help 119 Choose this option to build a kernel for release 2 or later of the 120 MIPS64 architecture. 121 122endchoice 123 124menu "OS boot interface" 125 126config MIPS_BOOT_CMDLINE_LEGACY 127 bool "Hand over legacy command line to Linux kernel" 128 default y 129 help 130 Enable this option if you want U-Boot to hand over the Yamon-style 131 command line to the kernel. All bootargs will be prepared as argc/argv 132 compatible list. The argument count (argc) is stored in register $a0. 133 The address of the argument list (argv) is stored in register $a1. 134 135config MIPS_BOOT_ENV_LEGACY 136 bool "Hand over legacy environment to Linux kernel" 137 default y 138 help 139 Enable this option if you want U-Boot to hand over the Yamon-style 140 environment to the kernel. Information like memory size, initrd 141 address and size will be prepared as zero-terminated key/value list. 142 The address of the enviroment is stored in register $a2. 143 144config MIPS_BOOT_FDT 145 bool "Hand over a flattened device tree to Linux kernel" 146 default n 147 help 148 Enable this option if you want U-Boot to hand over a flattened 149 device tree to the kernel. According to UHI register $a0 will be set 150 to -2 and the FDT address is stored in $a1. 151 152endmenu 153 154config SUPPORTS_BIG_ENDIAN 155 bool 156 157config SUPPORTS_LITTLE_ENDIAN 158 bool 159 160config SUPPORTS_CPU_MIPS32_R1 161 bool 162 163config SUPPORTS_CPU_MIPS32_R2 164 bool 165 166config SUPPORTS_CPU_MIPS64_R1 167 bool 168 169config SUPPORTS_CPU_MIPS64_R2 170 bool 171 172config CPU_MIPS32 173 bool 174 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 175 176config CPU_MIPS64 177 bool 178 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 179 180config 32BIT 181 bool 182 183config 64BIT 184 bool 185 186config SWAP_IO_SPACE 187 bool 188 189config SYS_MIPS_CACHE_INIT_RAM_LOAD 190 bool 191 192endif 193 194endmenu 195