1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L1_CACHE_SHIFT_6 32 select MIPS_L2_CACHE 33 select OF_CONTROL 34 select OF_ISA_BUS 35 select ROM_EXCEPTION_VECTORS 36 select SUPPORTS_BIG_ENDIAN 37 select SUPPORTS_CPU_MIPS32_R1 38 select SUPPORTS_CPU_MIPS32_R2 39 select SUPPORTS_CPU_MIPS32_R6 40 select SUPPORTS_CPU_MIPS64_R1 41 select SUPPORTS_CPU_MIPS64_R2 42 select SUPPORTS_CPU_MIPS64_R6 43 select SUPPORTS_LITTLE_ENDIAN 44 select SWAP_IO_SPACE 45 imply CMD_DM 46 47config TARGET_VCT 48 bool "Support vct" 49 select ROM_EXCEPTION_VECTORS 50 select SUPPORTS_BIG_ENDIAN 51 select SUPPORTS_CPU_MIPS32_R1 52 select SUPPORTS_CPU_MIPS32_R2 53 select SYS_MIPS_CACHE_INIT_RAM_LOAD 54 55config ARCH_ATH79 56 bool "Support QCA/Atheros ath79" 57 select DM 58 select OF_CONTROL 59 imply CMD_DM 60 61config ARCH_BMIPS 62 bool "Support BMIPS SoCs" 63 select CLK 64 select CPU 65 select DM 66 select OF_CONTROL 67 select RAM 68 select SYSRESET 69 imply CMD_DM 70 71config MACH_PIC32 72 bool "Support Microchip PIC32" 73 select DM 74 select OF_CONTROL 75 imply CMD_DM 76 77config TARGET_BOSTON 78 bool "Support Boston" 79 select DM 80 select DM_SERIAL 81 select MIPS_CM 82 select MIPS_L1_CACHE_SHIFT_6 83 select MIPS_L2_CACHE 84 select OF_BOARD_SETUP 85 select OF_CONTROL 86 select ROM_EXCEPTION_VECTORS 87 select SUPPORTS_BIG_ENDIAN 88 select SUPPORTS_CPU_MIPS32_R1 89 select SUPPORTS_CPU_MIPS32_R2 90 select SUPPORTS_CPU_MIPS32_R6 91 select SUPPORTS_CPU_MIPS64_R1 92 select SUPPORTS_CPU_MIPS64_R2 93 select SUPPORTS_CPU_MIPS64_R6 94 select SUPPORTS_LITTLE_ENDIAN 95 imply CMD_DM 96 97config TARGET_XILFPGA 98 bool "Support Imagination Xilfpga" 99 select DM 100 select DM_ETH 101 select DM_GPIO 102 select DM_SERIAL 103 select MIPS_L1_CACHE_SHIFT_4 104 select OF_CONTROL 105 select ROM_EXCEPTION_VECTORS 106 select SUPPORTS_CPU_MIPS32_R1 107 select SUPPORTS_CPU_MIPS32_R2 108 select SUPPORTS_LITTLE_ENDIAN 109 imply CMD_DM 110 help 111 This supports IMGTEC MIPSfpga platform 112 113endchoice 114 115source "board/imgtec/boston/Kconfig" 116source "board/imgtec/malta/Kconfig" 117source "board/imgtec/xilfpga/Kconfig" 118source "board/micronas/vct/Kconfig" 119source "board/qemu-mips/Kconfig" 120source "arch/mips/mach-ath79/Kconfig" 121source "arch/mips/mach-bmips/Kconfig" 122source "arch/mips/mach-pic32/Kconfig" 123 124if MIPS 125 126choice 127 prompt "Endianness selection" 128 help 129 Some MIPS boards can be configured for either little or big endian 130 byte order. These modes require different U-Boot images. In general there 131 is one preferred byteorder for a particular system but some systems are 132 just as commonly used in the one or the other endianness. 133 134config SYS_BIG_ENDIAN 135 bool "Big endian" 136 depends on SUPPORTS_BIG_ENDIAN 137 138config SYS_LITTLE_ENDIAN 139 bool "Little endian" 140 depends on SUPPORTS_LITTLE_ENDIAN 141 142endchoice 143 144choice 145 prompt "CPU selection" 146 default CPU_MIPS32_R2 147 148config CPU_MIPS32_R1 149 bool "MIPS32 Release 1" 150 depends on SUPPORTS_CPU_MIPS32_R1 151 select 32BIT 152 help 153 Choose this option to build an U-Boot for release 1 through 5 of the 154 MIPS32 architecture. 155 156config CPU_MIPS32_R2 157 bool "MIPS32 Release 2" 158 depends on SUPPORTS_CPU_MIPS32_R2 159 select 32BIT 160 help 161 Choose this option to build an U-Boot for release 2 through 5 of the 162 MIPS32 architecture. 163 164config CPU_MIPS32_R6 165 bool "MIPS32 Release 6" 166 depends on SUPPORTS_CPU_MIPS32_R6 167 select 32BIT 168 help 169 Choose this option to build an U-Boot for release 6 or later of the 170 MIPS32 architecture. 171 172config CPU_MIPS64_R1 173 bool "MIPS64 Release 1" 174 depends on SUPPORTS_CPU_MIPS64_R1 175 select 64BIT 176 help 177 Choose this option to build a kernel for release 1 through 5 of the 178 MIPS64 architecture. 179 180config CPU_MIPS64_R2 181 bool "MIPS64 Release 2" 182 depends on SUPPORTS_CPU_MIPS64_R2 183 select 64BIT 184 help 185 Choose this option to build a kernel for release 2 through 5 of the 186 MIPS64 architecture. 187 188config CPU_MIPS64_R6 189 bool "MIPS64 Release 6" 190 depends on SUPPORTS_CPU_MIPS64_R6 191 select 64BIT 192 help 193 Choose this option to build a kernel for release 6 or later of the 194 MIPS64 architecture. 195 196endchoice 197 198menu "General setup" 199 200config ROM_EXCEPTION_VECTORS 201 bool "Build U-Boot image with exception vectors" 202 help 203 Enable this to include exception vectors in the U-Boot image. This is 204 required if the U-Boot entry point is equal to the address of the 205 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 206 U-Boot booted from parallel NOR flash). 207 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 208 In that case the image size will be reduced by 0x500 bytes. 209 210config MIPS_CM_BASE 211 hex "MIPS CM GCR Base Address" 212 depends on MIPS_CM 213 default 0x16100000 if TARGET_BOSTON 214 default 0x1fbf8000 215 help 216 The physical base address at which to map the MIPS Coherence Manager 217 Global Configuration Registers (GCRs). This should be set such that 218 the GCRs occupy a region of the physical address space which is 219 otherwise unused, or at minimum that software doesn't need to access. 220 221endmenu 222 223menu "OS boot interface" 224 225config MIPS_BOOT_CMDLINE_LEGACY 226 bool "Hand over legacy command line to Linux kernel" 227 default y 228 help 229 Enable this option if you want U-Boot to hand over the Yamon-style 230 command line to the kernel. All bootargs will be prepared as argc/argv 231 compatible list. The argument count (argc) is stored in register $a0. 232 The address of the argument list (argv) is stored in register $a1. 233 234config MIPS_BOOT_ENV_LEGACY 235 bool "Hand over legacy environment to Linux kernel" 236 default y 237 help 238 Enable this option if you want U-Boot to hand over the Yamon-style 239 environment to the kernel. Information like memory size, initrd 240 address and size will be prepared as zero-terminated key/value list. 241 The address of the environment is stored in register $a2. 242 243config MIPS_BOOT_FDT 244 bool "Hand over a flattened device tree to Linux kernel" 245 default n 246 help 247 Enable this option if you want U-Boot to hand over a flattened 248 device tree to the kernel. According to UHI register $a0 will be set 249 to -2 and the FDT address is stored in $a1. 250 251endmenu 252 253config SUPPORTS_BIG_ENDIAN 254 bool 255 256config SUPPORTS_LITTLE_ENDIAN 257 bool 258 259config SUPPORTS_CPU_MIPS32_R1 260 bool 261 262config SUPPORTS_CPU_MIPS32_R2 263 bool 264 265config SUPPORTS_CPU_MIPS32_R6 266 bool 267 268config SUPPORTS_CPU_MIPS64_R1 269 bool 270 271config SUPPORTS_CPU_MIPS64_R2 272 bool 273 274config SUPPORTS_CPU_MIPS64_R6 275 bool 276 277config CPU_MIPS32 278 bool 279 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 280 281config CPU_MIPS64 282 bool 283 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 284 285config MIPS_TUNE_4KC 286 bool 287 288config MIPS_TUNE_14KC 289 bool 290 291config MIPS_TUNE_24KC 292 bool 293 294config MIPS_TUNE_34KC 295 bool 296 297config MIPS_TUNE_74KC 298 bool 299 300config 32BIT 301 bool 302 303config 64BIT 304 bool 305 306config SWAP_IO_SPACE 307 bool 308 309config SYS_MIPS_CACHE_INIT_RAM_LOAD 310 bool 311 312config MIPS_INIT_STACK_IN_SRAM 313 bool 314 default n 315 help 316 Select this if the initial stack frame could be setup in SRAM. 317 Normally the initial stack frame is set up in DRAM which is often 318 only available after lowlevel_init. With this option the initial 319 stack frame and the early C environment is set up before 320 lowlevel_init. Thus lowlevel_init does not need to be implemented 321 in assembler. 322 323config SYS_DCACHE_SIZE 324 int 325 default 0 326 help 327 The total size of the L1 Dcache, if known at compile time. 328 329config SYS_DCACHE_LINE_SIZE 330 int 331 default 0 332 help 333 The size of L1 Dcache lines, if known at compile time. 334 335config SYS_ICACHE_SIZE 336 int 337 default 0 338 help 339 The total size of the L1 ICache, if known at compile time. 340 341config SYS_ICACHE_LINE_SIZE 342 int 343 default 0 344 help 345 The size of L1 Icache lines, if known at compile time. 346 347config SYS_CACHE_SIZE_AUTO 348 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 349 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 350 help 351 Select this (or let it be auto-selected by not defining any cache 352 sizes) in order to allow U-Boot to automatically detect the sizes 353 of caches at runtime. This has a small cost in code size & runtime 354 so if you know the cache configuration for your system at compile 355 time it would be beneficial to configure it. 356 357config MIPS_L1_CACHE_SHIFT_4 358 bool 359 360config MIPS_L1_CACHE_SHIFT_5 361 bool 362 363config MIPS_L1_CACHE_SHIFT_6 364 bool 365 366config MIPS_L1_CACHE_SHIFT_7 367 bool 368 369config MIPS_L1_CACHE_SHIFT 370 int 371 default "7" if MIPS_L1_CACHE_SHIFT_7 372 default "6" if MIPS_L1_CACHE_SHIFT_6 373 default "5" if MIPS_L1_CACHE_SHIFT_5 374 default "4" if MIPS_L1_CACHE_SHIFT_4 375 default "5" 376 377config MIPS_L2_CACHE 378 bool 379 help 380 Select this if your system includes an L2 cache and you want U-Boot 381 to initialise & maintain it. 382 383config DYNAMIC_IO_PORT_BASE 384 bool 385 386config MIPS_CM 387 bool 388 help 389 Select this if your system contains a MIPS Coherence Manager and you 390 wish U-Boot to configure it or make use of it to retrieve system 391 information such as cache configuration. 392 393endif 394 395endmenu 396