1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L1_CACHE_SHIFT_6 32 select MIPS_L2_CACHE 33 select OF_CONTROL 34 select OF_ISA_BUS 35 select ROM_EXCEPTION_VECTORS 36 select SUPPORTS_BIG_ENDIAN 37 select SUPPORTS_CPU_MIPS32_R1 38 select SUPPORTS_CPU_MIPS32_R2 39 select SUPPORTS_CPU_MIPS32_R6 40 select SUPPORTS_CPU_MIPS64_R1 41 select SUPPORTS_CPU_MIPS64_R2 42 select SUPPORTS_CPU_MIPS64_R6 43 select SUPPORTS_LITTLE_ENDIAN 44 select SWAP_IO_SPACE 45 imply CMD_DM 46 47config TARGET_VCT 48 bool "Support vct" 49 select ROM_EXCEPTION_VECTORS 50 select SUPPORTS_BIG_ENDIAN 51 select SUPPORTS_CPU_MIPS32_R1 52 select SUPPORTS_CPU_MIPS32_R2 53 select SYS_MIPS_CACHE_INIT_RAM_LOAD 54 55config TARGET_DBAU1X00 56 bool "Support dbau1x00" 57 select MIPS_TUNE_4KC 58 select ROM_EXCEPTION_VECTORS 59 select SUPPORTS_BIG_ENDIAN 60 select SUPPORTS_CPU_MIPS32_R1 61 select SUPPORTS_CPU_MIPS32_R2 62 select SUPPORTS_LITTLE_ENDIAN 63 select SYS_MIPS_CACHE_INIT_RAM_LOAD 64 65config TARGET_PB1X00 66 bool "Support pb1x00" 67 select MIPS_TUNE_4KC 68 select ROM_EXCEPTION_VECTORS 69 select SUPPORTS_CPU_MIPS32_R1 70 select SUPPORTS_CPU_MIPS32_R2 71 select SUPPORTS_LITTLE_ENDIAN 72 select SYS_MIPS_CACHE_INIT_RAM_LOAD 73 74config ARCH_ATH79 75 bool "Support QCA/Atheros ath79" 76 select DM 77 select OF_CONTROL 78 imply CMD_DM 79 80config ARCH_BMIPS 81 bool "Support BMIPS SoCs" 82 select CLK 83 select CPU 84 select DM 85 select OF_CONTROL 86 select RAM 87 select SYSRESET 88 imply CMD_DM 89 90config MACH_PIC32 91 bool "Support Microchip PIC32" 92 select DM 93 select OF_CONTROL 94 imply CMD_DM 95 96config TARGET_BOSTON 97 bool "Support Boston" 98 select DM 99 select DM_SERIAL 100 select MIPS_CM 101 select MIPS_L1_CACHE_SHIFT_6 102 select MIPS_L2_CACHE 103 select OF_BOARD_SETUP 104 select OF_CONTROL 105 select ROM_EXCEPTION_VECTORS 106 select SUPPORTS_BIG_ENDIAN 107 select SUPPORTS_CPU_MIPS32_R1 108 select SUPPORTS_CPU_MIPS32_R2 109 select SUPPORTS_CPU_MIPS32_R6 110 select SUPPORTS_CPU_MIPS64_R1 111 select SUPPORTS_CPU_MIPS64_R2 112 select SUPPORTS_CPU_MIPS64_R6 113 select SUPPORTS_LITTLE_ENDIAN 114 imply CMD_DM 115 116config TARGET_XILFPGA 117 bool "Support Imagination Xilfpga" 118 select DM 119 select DM_ETH 120 select DM_GPIO 121 select DM_SERIAL 122 select MIPS_L1_CACHE_SHIFT_4 123 select OF_CONTROL 124 select ROM_EXCEPTION_VECTORS 125 select SUPPORTS_CPU_MIPS32_R1 126 select SUPPORTS_CPU_MIPS32_R2 127 select SUPPORTS_LITTLE_ENDIAN 128 imply CMD_DM 129 help 130 This supports IMGTEC MIPSfpga platform 131 132endchoice 133 134source "board/dbau1x00/Kconfig" 135source "board/imgtec/boston/Kconfig" 136source "board/imgtec/malta/Kconfig" 137source "board/imgtec/xilfpga/Kconfig" 138source "board/micronas/vct/Kconfig" 139source "board/pb1x00/Kconfig" 140source "board/qemu-mips/Kconfig" 141source "arch/mips/mach-ath79/Kconfig" 142source "arch/mips/mach-bmips/Kconfig" 143source "arch/mips/mach-pic32/Kconfig" 144 145if MIPS 146 147choice 148 prompt "Endianness selection" 149 help 150 Some MIPS boards can be configured for either little or big endian 151 byte order. These modes require different U-Boot images. In general there 152 is one preferred byteorder for a particular system but some systems are 153 just as commonly used in the one or the other endianness. 154 155config SYS_BIG_ENDIAN 156 bool "Big endian" 157 depends on SUPPORTS_BIG_ENDIAN 158 159config SYS_LITTLE_ENDIAN 160 bool "Little endian" 161 depends on SUPPORTS_LITTLE_ENDIAN 162 163endchoice 164 165choice 166 prompt "CPU selection" 167 default CPU_MIPS32_R2 168 169config CPU_MIPS32_R1 170 bool "MIPS32 Release 1" 171 depends on SUPPORTS_CPU_MIPS32_R1 172 select 32BIT 173 help 174 Choose this option to build an U-Boot for release 1 through 5 of the 175 MIPS32 architecture. 176 177config CPU_MIPS32_R2 178 bool "MIPS32 Release 2" 179 depends on SUPPORTS_CPU_MIPS32_R2 180 select 32BIT 181 help 182 Choose this option to build an U-Boot for release 2 through 5 of the 183 MIPS32 architecture. 184 185config CPU_MIPS32_R6 186 bool "MIPS32 Release 6" 187 depends on SUPPORTS_CPU_MIPS32_R6 188 select 32BIT 189 help 190 Choose this option to build an U-Boot for release 6 or later of the 191 MIPS32 architecture. 192 193config CPU_MIPS64_R1 194 bool "MIPS64 Release 1" 195 depends on SUPPORTS_CPU_MIPS64_R1 196 select 64BIT 197 help 198 Choose this option to build a kernel for release 1 through 5 of the 199 MIPS64 architecture. 200 201config CPU_MIPS64_R2 202 bool "MIPS64 Release 2" 203 depends on SUPPORTS_CPU_MIPS64_R2 204 select 64BIT 205 help 206 Choose this option to build a kernel for release 2 through 5 of the 207 MIPS64 architecture. 208 209config CPU_MIPS64_R6 210 bool "MIPS64 Release 6" 211 depends on SUPPORTS_CPU_MIPS64_R6 212 select 64BIT 213 help 214 Choose this option to build a kernel for release 6 or later of the 215 MIPS64 architecture. 216 217endchoice 218 219menu "General setup" 220 221config ROM_EXCEPTION_VECTORS 222 bool "Build U-Boot image with exception vectors" 223 help 224 Enable this to include exception vectors in the U-Boot image. This is 225 required if the U-Boot entry point is equal to the address of the 226 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 227 U-Boot booted from parallel NOR flash). 228 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 229 In that case the image size will be reduced by 0x500 bytes. 230 231config MIPS_CM_BASE 232 hex "MIPS CM GCR Base Address" 233 depends on MIPS_CM 234 default 0x16100000 if TARGET_BOSTON 235 default 0x1fbf8000 236 help 237 The physical base address at which to map the MIPS Coherence Manager 238 Global Configuration Registers (GCRs). This should be set such that 239 the GCRs occupy a region of the physical address space which is 240 otherwise unused, or at minimum that software doesn't need to access. 241 242endmenu 243 244menu "OS boot interface" 245 246config MIPS_BOOT_CMDLINE_LEGACY 247 bool "Hand over legacy command line to Linux kernel" 248 default y 249 help 250 Enable this option if you want U-Boot to hand over the Yamon-style 251 command line to the kernel. All bootargs will be prepared as argc/argv 252 compatible list. The argument count (argc) is stored in register $a0. 253 The address of the argument list (argv) is stored in register $a1. 254 255config MIPS_BOOT_ENV_LEGACY 256 bool "Hand over legacy environment to Linux kernel" 257 default y 258 help 259 Enable this option if you want U-Boot to hand over the Yamon-style 260 environment to the kernel. Information like memory size, initrd 261 address and size will be prepared as zero-terminated key/value list. 262 The address of the environment is stored in register $a2. 263 264config MIPS_BOOT_FDT 265 bool "Hand over a flattened device tree to Linux kernel" 266 default n 267 help 268 Enable this option if you want U-Boot to hand over a flattened 269 device tree to the kernel. According to UHI register $a0 will be set 270 to -2 and the FDT address is stored in $a1. 271 272endmenu 273 274config SUPPORTS_BIG_ENDIAN 275 bool 276 277config SUPPORTS_LITTLE_ENDIAN 278 bool 279 280config SUPPORTS_CPU_MIPS32_R1 281 bool 282 283config SUPPORTS_CPU_MIPS32_R2 284 bool 285 286config SUPPORTS_CPU_MIPS32_R6 287 bool 288 289config SUPPORTS_CPU_MIPS64_R1 290 bool 291 292config SUPPORTS_CPU_MIPS64_R2 293 bool 294 295config SUPPORTS_CPU_MIPS64_R6 296 bool 297 298config CPU_MIPS32 299 bool 300 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 301 302config CPU_MIPS64 303 bool 304 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 305 306config MIPS_TUNE_4KC 307 bool 308 309config MIPS_TUNE_14KC 310 bool 311 312config MIPS_TUNE_24KC 313 bool 314 315config MIPS_TUNE_34KC 316 bool 317 318config MIPS_TUNE_74KC 319 bool 320 321config 32BIT 322 bool 323 324config 64BIT 325 bool 326 327config SWAP_IO_SPACE 328 bool 329 330config SYS_MIPS_CACHE_INIT_RAM_LOAD 331 bool 332 333config MIPS_INIT_STACK_IN_SRAM 334 bool 335 default n 336 help 337 Select this if the initial stack frame could be setup in SRAM. 338 Normally the initial stack frame is set up in DRAM which is often 339 only available after lowlevel_init. With this option the initial 340 stack frame and the early C environment is set up before 341 lowlevel_init. Thus lowlevel_init does not need to be implemented 342 in assembler. 343 344config SYS_DCACHE_SIZE 345 int 346 default 0 347 help 348 The total size of the L1 Dcache, if known at compile time. 349 350config SYS_DCACHE_LINE_SIZE 351 int 352 default 0 353 help 354 The size of L1 Dcache lines, if known at compile time. 355 356config SYS_ICACHE_SIZE 357 int 358 default 0 359 help 360 The total size of the L1 ICache, if known at compile time. 361 362config SYS_ICACHE_LINE_SIZE 363 int 364 default 0 365 help 366 The size of L1 Icache lines, if known at compile time. 367 368config SYS_CACHE_SIZE_AUTO 369 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 370 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 371 help 372 Select this (or let it be auto-selected by not defining any cache 373 sizes) in order to allow U-Boot to automatically detect the sizes 374 of caches at runtime. This has a small cost in code size & runtime 375 so if you know the cache configuration for your system at compile 376 time it would be beneficial to configure it. 377 378config MIPS_L1_CACHE_SHIFT_4 379 bool 380 381config MIPS_L1_CACHE_SHIFT_5 382 bool 383 384config MIPS_L1_CACHE_SHIFT_6 385 bool 386 387config MIPS_L1_CACHE_SHIFT_7 388 bool 389 390config MIPS_L1_CACHE_SHIFT 391 int 392 default "7" if MIPS_L1_CACHE_SHIFT_7 393 default "6" if MIPS_L1_CACHE_SHIFT_6 394 default "5" if MIPS_L1_CACHE_SHIFT_5 395 default "4" if MIPS_L1_CACHE_SHIFT_4 396 default "5" 397 398config MIPS_L2_CACHE 399 bool 400 help 401 Select this if your system includes an L2 cache and you want U-Boot 402 to initialise & maintain it. 403 404config DYNAMIC_IO_PORT_BASE 405 bool 406 407config MIPS_CM 408 bool 409 help 410 Select this if your system contains a MIPS Coherence Manager and you 411 wish U-Boot to configure it or make use of it to retrieve system 412 information such as cache configuration. 413 414endif 415 416endmenu 417