1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 24config TARGET_MALTA 25 bool "Support malta" 26 select DM 27 select DM_SERIAL 28 select DYNAMIC_IO_PORT_BASE 29 select OF_CONTROL 30 select OF_ISA_BUS 31 select SUPPORTS_BIG_ENDIAN 32 select SUPPORTS_LITTLE_ENDIAN 33 select SUPPORTS_CPU_MIPS32_R1 34 select SUPPORTS_CPU_MIPS32_R2 35 select SUPPORTS_CPU_MIPS32_R6 36 select SWAP_IO_SPACE 37 select MIPS_L1_CACHE_SHIFT_6 38 39config TARGET_VCT 40 bool "Support vct" 41 select SUPPORTS_BIG_ENDIAN 42 select SUPPORTS_CPU_MIPS32_R1 43 select SUPPORTS_CPU_MIPS32_R2 44 select SYS_MIPS_CACHE_INIT_RAM_LOAD 45 46config TARGET_DBAU1X00 47 bool "Support dbau1x00" 48 select SUPPORTS_BIG_ENDIAN 49 select SUPPORTS_LITTLE_ENDIAN 50 select SUPPORTS_CPU_MIPS32_R1 51 select SUPPORTS_CPU_MIPS32_R2 52 select SYS_MIPS_CACHE_INIT_RAM_LOAD 53 select MIPS_TUNE_4KC 54 55config TARGET_PB1X00 56 bool "Support pb1x00" 57 select SUPPORTS_LITTLE_ENDIAN 58 select SUPPORTS_CPU_MIPS32_R1 59 select SUPPORTS_CPU_MIPS32_R2 60 select SYS_MIPS_CACHE_INIT_RAM_LOAD 61 select MIPS_TUNE_4KC 62 63config ARCH_ATH79 64 bool "Support QCA/Atheros ath79" 65 select OF_CONTROL 66 select DM 67 68config MACH_PIC32 69 bool "Support Microchip PIC32" 70 select OF_CONTROL 71 select DM 72 73endchoice 74 75source "board/dbau1x00/Kconfig" 76source "board/imgtec/malta/Kconfig" 77source "board/micronas/vct/Kconfig" 78source "board/pb1x00/Kconfig" 79source "board/qemu-mips/Kconfig" 80source "arch/mips/mach-ath79/Kconfig" 81source "arch/mips/mach-pic32/Kconfig" 82 83if MIPS 84 85choice 86 prompt "Endianness selection" 87 help 88 Some MIPS boards can be configured for either little or big endian 89 byte order. These modes require different U-Boot images. In general there 90 is one preferred byteorder for a particular system but some systems are 91 just as commonly used in the one or the other endianness. 92 93config SYS_BIG_ENDIAN 94 bool "Big endian" 95 depends on SUPPORTS_BIG_ENDIAN 96 97config SYS_LITTLE_ENDIAN 98 bool "Little endian" 99 depends on SUPPORTS_LITTLE_ENDIAN 100 101endchoice 102 103choice 104 prompt "CPU selection" 105 default CPU_MIPS32_R2 106 107config CPU_MIPS32_R1 108 bool "MIPS32 Release 1" 109 depends on SUPPORTS_CPU_MIPS32_R1 110 select 32BIT 111 help 112 Choose this option to build an U-Boot for release 1 through 5 of the 113 MIPS32 architecture. 114 115config CPU_MIPS32_R2 116 bool "MIPS32 Release 2" 117 depends on SUPPORTS_CPU_MIPS32_R2 118 select 32BIT 119 help 120 Choose this option to build an U-Boot for release 2 through 5 of the 121 MIPS32 architecture. 122 123config CPU_MIPS32_R6 124 bool "MIPS32 Release 6" 125 depends on SUPPORTS_CPU_MIPS32_R6 126 select 32BIT 127 help 128 Choose this option to build an U-Boot for release 6 or later of the 129 MIPS32 architecture. 130 131config CPU_MIPS64_R1 132 bool "MIPS64 Release 1" 133 depends on SUPPORTS_CPU_MIPS64_R1 134 select 64BIT 135 help 136 Choose this option to build a kernel for release 1 through 5 of the 137 MIPS64 architecture. 138 139config CPU_MIPS64_R2 140 bool "MIPS64 Release 2" 141 depends on SUPPORTS_CPU_MIPS64_R2 142 select 64BIT 143 help 144 Choose this option to build a kernel for release 2 through 5 of the 145 MIPS64 architecture. 146 147config CPU_MIPS64_R6 148 bool "MIPS64 Release 6" 149 depends on SUPPORTS_CPU_MIPS64_R6 150 select 64BIT 151 help 152 Choose this option to build a kernel for release 6 or later of the 153 MIPS64 architecture. 154 155endchoice 156 157menu "OS boot interface" 158 159config MIPS_BOOT_CMDLINE_LEGACY 160 bool "Hand over legacy command line to Linux kernel" 161 default y 162 help 163 Enable this option if you want U-Boot to hand over the Yamon-style 164 command line to the kernel. All bootargs will be prepared as argc/argv 165 compatible list. The argument count (argc) is stored in register $a0. 166 The address of the argument list (argv) is stored in register $a1. 167 168config MIPS_BOOT_ENV_LEGACY 169 bool "Hand over legacy environment to Linux kernel" 170 default y 171 help 172 Enable this option if you want U-Boot to hand over the Yamon-style 173 environment to the kernel. Information like memory size, initrd 174 address and size will be prepared as zero-terminated key/value list. 175 The address of the environment is stored in register $a2. 176 177config MIPS_BOOT_FDT 178 bool "Hand over a flattened device tree to Linux kernel" 179 default n 180 help 181 Enable this option if you want U-Boot to hand over a flattened 182 device tree to the kernel. According to UHI register $a0 will be set 183 to -2 and the FDT address is stored in $a1. 184 185endmenu 186 187config SUPPORTS_BIG_ENDIAN 188 bool 189 190config SUPPORTS_LITTLE_ENDIAN 191 bool 192 193config SUPPORTS_CPU_MIPS32_R1 194 bool 195 196config SUPPORTS_CPU_MIPS32_R2 197 bool 198 199config SUPPORTS_CPU_MIPS32_R6 200 bool 201 202config SUPPORTS_CPU_MIPS64_R1 203 bool 204 205config SUPPORTS_CPU_MIPS64_R2 206 bool 207 208config SUPPORTS_CPU_MIPS64_R6 209 bool 210 211config CPU_MIPS32 212 bool 213 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 214 215config CPU_MIPS64 216 bool 217 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 218 219config MIPS_TUNE_4KC 220 bool 221 222config MIPS_TUNE_14KC 223 bool 224 225config MIPS_TUNE_24KC 226 bool 227 228config MIPS_TUNE_74KC 229 bool 230 231config 32BIT 232 bool 233 234config 64BIT 235 bool 236 237config SWAP_IO_SPACE 238 bool 239 240config SYS_MIPS_CACHE_INIT_RAM_LOAD 241 bool 242 243config MIPS_L1_CACHE_SHIFT_4 244 bool 245 246config MIPS_L1_CACHE_SHIFT_5 247 bool 248 249config MIPS_L1_CACHE_SHIFT_6 250 bool 251 252config MIPS_L1_CACHE_SHIFT_7 253 bool 254 255config MIPS_L1_CACHE_SHIFT 256 int 257 default "7" if MIPS_L1_CACHE_SHIFT_7 258 default "6" if MIPS_L1_CACHE_SHIFT_6 259 default "5" if MIPS_L1_CACHE_SHIFT_5 260 default "4" if MIPS_L1_CACHE_SHIFT_4 261 default "5" 262 263config DYNAMIC_IO_PORT_BASE 264 bool 265 266endif 267 268endmenu 269