xref: /openbmc/u-boot/arch/mips/Kconfig (revision 21845825)
1menu "MIPS architecture"
2	depends on MIPS
3
4config SYS_ARCH
5	default "mips"
6
7config SYS_CPU
8	default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
9	default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
10
11choice
12	prompt "Target select"
13	optional
14
15config TARGET_QEMU_MIPS
16	bool "Support qemu-mips"
17	select SUPPORTS_BIG_ENDIAN
18	select SUPPORTS_LITTLE_ENDIAN
19	select SUPPORTS_CPU_MIPS32_R1
20	select SUPPORTS_CPU_MIPS32_R2
21	select SUPPORTS_CPU_MIPS64_R1
22	select SUPPORTS_CPU_MIPS64_R2
23
24config TARGET_MALTA
25	bool "Support malta"
26	select DYNAMIC_IO_PORT_BASE
27	select SUPPORTS_BIG_ENDIAN
28	select SUPPORTS_LITTLE_ENDIAN
29	select SUPPORTS_CPU_MIPS32_R1
30	select SUPPORTS_CPU_MIPS32_R2
31	select SWAP_IO_SPACE
32	select MIPS_L1_CACHE_SHIFT_6
33
34config TARGET_VCT
35	bool "Support vct"
36	select SUPPORTS_BIG_ENDIAN
37	select SUPPORTS_CPU_MIPS32_R1
38	select SUPPORTS_CPU_MIPS32_R2
39	select SYS_MIPS_CACHE_INIT_RAM_LOAD
40
41config TARGET_DBAU1X00
42	bool "Support dbau1x00"
43	select SUPPORTS_BIG_ENDIAN
44	select SUPPORTS_LITTLE_ENDIAN
45	select SUPPORTS_CPU_MIPS32_R1
46	select SUPPORTS_CPU_MIPS32_R2
47	select SYS_MIPS_CACHE_INIT_RAM_LOAD
48	select MIPS_TUNE_4KC
49
50config TARGET_PB1X00
51	bool "Support pb1x00"
52	select SUPPORTS_LITTLE_ENDIAN
53	select SUPPORTS_CPU_MIPS32_R1
54	select SUPPORTS_CPU_MIPS32_R2
55	select SYS_MIPS_CACHE_INIT_RAM_LOAD
56	select MIPS_TUNE_4KC
57
58config MACH_PIC32
59	bool "Support Microchip PIC32"
60	select OF_CONTROL
61	select DM
62
63endchoice
64
65source "board/dbau1x00/Kconfig"
66source "board/imgtec/malta/Kconfig"
67source "board/micronas/vct/Kconfig"
68source "board/pb1x00/Kconfig"
69source "board/qemu-mips/Kconfig"
70source "arch/mips/mach-pic32/Kconfig"
71
72if MIPS
73
74choice
75	prompt "Endianness selection"
76	help
77	  Some MIPS boards can be configured for either little or big endian
78	  byte order. These modes require different U-Boot images. In general there
79	  is one preferred byteorder for a particular system but some systems are
80	  just as commonly used in the one or the other endianness.
81
82config SYS_BIG_ENDIAN
83	bool "Big endian"
84	depends on SUPPORTS_BIG_ENDIAN
85
86config SYS_LITTLE_ENDIAN
87	bool "Little endian"
88	depends on SUPPORTS_LITTLE_ENDIAN
89
90endchoice
91
92choice
93	prompt "CPU selection"
94	default CPU_MIPS32_R2
95
96config CPU_MIPS32_R1
97	bool "MIPS32 Release 1"
98	depends on SUPPORTS_CPU_MIPS32_R1
99	select 32BIT
100	help
101	  Choose this option to build an U-Boot for release 1 or later of the
102	  MIPS32 architecture.
103
104config CPU_MIPS32_R2
105	bool "MIPS32 Release 2"
106	depends on SUPPORTS_CPU_MIPS32_R2
107	select 32BIT
108	help
109	  Choose this option to build an U-Boot for release 2 or later of the
110	  MIPS32 architecture.
111
112config CPU_MIPS64_R1
113	bool "MIPS64 Release 1"
114	depends on SUPPORTS_CPU_MIPS64_R1
115	select 64BIT
116	help
117	  Choose this option to build a kernel for release 1 or later of the
118	  MIPS64 architecture.
119
120config CPU_MIPS64_R2
121	bool "MIPS64 Release 2"
122	depends on SUPPORTS_CPU_MIPS64_R2
123	select 64BIT
124	help
125	  Choose this option to build a kernel for release 2 or later of the
126	  MIPS64 architecture.
127
128endchoice
129
130menu "OS boot interface"
131
132config MIPS_BOOT_CMDLINE_LEGACY
133	bool "Hand over legacy command line to Linux kernel"
134	default y
135	help
136	  Enable this option if you want U-Boot to hand over the Yamon-style
137	  command line to the kernel. All bootargs will be prepared as argc/argv
138	  compatible list. The argument count (argc) is stored in register $a0.
139	  The address of the argument list (argv) is stored in register $a1.
140
141config MIPS_BOOT_ENV_LEGACY
142	bool "Hand over legacy environment to Linux kernel"
143	default y
144	help
145	  Enable this option if you want U-Boot to hand over the Yamon-style
146	  environment to the kernel. Information like memory size, initrd
147	  address and size will be prepared as zero-terminated key/value list.
148	  The address of the enviroment is stored in register $a2.
149
150config MIPS_BOOT_FDT
151	bool "Hand over a flattened device tree to Linux kernel"
152	default n
153	help
154	  Enable this option if you want U-Boot to hand over a flattened
155	  device tree to the kernel. According to UHI register $a0 will be set
156	  to -2 and the FDT address is stored in $a1.
157
158endmenu
159
160config SUPPORTS_BIG_ENDIAN
161	bool
162
163config SUPPORTS_LITTLE_ENDIAN
164	bool
165
166config SUPPORTS_CPU_MIPS32_R1
167	bool
168
169config SUPPORTS_CPU_MIPS32_R2
170	bool
171
172config SUPPORTS_CPU_MIPS64_R1
173	bool
174
175config SUPPORTS_CPU_MIPS64_R2
176	bool
177
178config CPU_MIPS32
179	bool
180	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
181
182config CPU_MIPS64
183	bool
184	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
185
186config MIPS_TUNE_4KC
187	bool
188
189config MIPS_TUNE_14KC
190	bool
191
192config MIPS_TUNE_24KC
193	bool
194
195config 32BIT
196	bool
197
198config 64BIT
199	bool
200
201config SWAP_IO_SPACE
202	bool
203
204config SYS_MIPS_CACHE_INIT_RAM_LOAD
205	bool
206
207config MIPS_L1_CACHE_SHIFT_4
208	bool
209
210config MIPS_L1_CACHE_SHIFT_5
211	bool
212
213config MIPS_L1_CACHE_SHIFT_6
214	bool
215
216config MIPS_L1_CACHE_SHIFT_7
217	bool
218
219config MIPS_L1_CACHE_SHIFT
220	int
221	default "7" if MIPS_L1_CACHE_SHIFT_7
222	default "6" if MIPS_L1_CACHE_SHIFT_6
223	default "5" if MIPS_L1_CACHE_SHIFT_5
224	default "4" if MIPS_L1_CACHE_SHIFT_4
225	default "5"
226
227config DYNAMIC_IO_PORT_BASE
228	bool
229
230endif
231
232endmenu
233