1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_INSERT_BOOT_CONFIG 32 select MIPS_L1_CACHE_SHIFT_6 33 select MIPS_L2_CACHE 34 select OF_CONTROL 35 select OF_ISA_BUS 36 select ROM_EXCEPTION_VECTORS 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SUPPORTS_CPU_MIPS32_R6 41 select SUPPORTS_CPU_MIPS64_R1 42 select SUPPORTS_CPU_MIPS64_R2 43 select SUPPORTS_CPU_MIPS64_R6 44 select SUPPORTS_LITTLE_ENDIAN 45 select SWAP_IO_SPACE 46 imply CMD_DM 47 48config TARGET_VCT 49 bool "Support vct" 50 select ROM_EXCEPTION_VECTORS 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_CPU_MIPS32_R1 53 select SUPPORTS_CPU_MIPS32_R2 54 select SYS_MIPS_CACHE_INIT_RAM_LOAD 55 56config ARCH_ATH79 57 bool "Support QCA/Atheros ath79" 58 select DM 59 select OF_CONTROL 60 imply CMD_DM 61 62config ARCH_BMIPS 63 bool "Support BMIPS SoCs" 64 select CLK 65 select CPU 66 select DM 67 select OF_CONTROL 68 select RAM 69 select SYSRESET 70 imply CMD_DM 71 72config ARCH_MT7620 73 bool "Support MT7620/7688 SoCs" 74 imply CMD_DM 75 select DISPLAY_CPUINFO 76 select DM 77 select DM_SERIAL 78 imply DM_SPI 79 imply DM_SPI_FLASH 80 select MIPS_TUNE_24KC 81 select OF_CONTROL 82 select ROM_EXCEPTION_VECTORS 83 select SUPPORTS_CPU_MIPS32_R1 84 select SUPPORTS_CPU_MIPS32_R2 85 select SUPPORTS_LITTLE_ENDIAN 86 select SYSRESET 87 88config MACH_PIC32 89 bool "Support Microchip PIC32" 90 select DM 91 select OF_CONTROL 92 imply CMD_DM 93 94config TARGET_BOSTON 95 bool "Support Boston" 96 select DM 97 select DM_SERIAL 98 select MIPS_CM 99 select MIPS_L1_CACHE_SHIFT_6 100 select MIPS_L2_CACHE 101 select OF_BOARD_SETUP 102 select OF_CONTROL 103 select ROM_EXCEPTION_VECTORS 104 select SUPPORTS_BIG_ENDIAN 105 select SUPPORTS_CPU_MIPS32_R1 106 select SUPPORTS_CPU_MIPS32_R2 107 select SUPPORTS_CPU_MIPS32_R6 108 select SUPPORTS_CPU_MIPS64_R1 109 select SUPPORTS_CPU_MIPS64_R2 110 select SUPPORTS_CPU_MIPS64_R6 111 select SUPPORTS_LITTLE_ENDIAN 112 imply CMD_DM 113 114config TARGET_XILFPGA 115 bool "Support Imagination Xilfpga" 116 select DM 117 select DM_ETH 118 select DM_GPIO 119 select DM_SERIAL 120 select MIPS_L1_CACHE_SHIFT_4 121 select OF_CONTROL 122 select ROM_EXCEPTION_VECTORS 123 select SUPPORTS_CPU_MIPS32_R1 124 select SUPPORTS_CPU_MIPS32_R2 125 select SUPPORTS_LITTLE_ENDIAN 126 imply CMD_DM 127 help 128 This supports IMGTEC MIPSfpga platform 129 130endchoice 131 132source "board/imgtec/boston/Kconfig" 133source "board/imgtec/malta/Kconfig" 134source "board/imgtec/xilfpga/Kconfig" 135source "board/micronas/vct/Kconfig" 136source "board/qemu-mips/Kconfig" 137source "arch/mips/mach-ath79/Kconfig" 138source "arch/mips/mach-bmips/Kconfig" 139source "arch/mips/mach-pic32/Kconfig" 140source "arch/mips/mach-mt7620/Kconfig" 141 142if MIPS 143 144choice 145 prompt "Endianness selection" 146 help 147 Some MIPS boards can be configured for either little or big endian 148 byte order. These modes require different U-Boot images. In general there 149 is one preferred byteorder for a particular system but some systems are 150 just as commonly used in the one or the other endianness. 151 152config SYS_BIG_ENDIAN 153 bool "Big endian" 154 depends on SUPPORTS_BIG_ENDIAN 155 156config SYS_LITTLE_ENDIAN 157 bool "Little endian" 158 depends on SUPPORTS_LITTLE_ENDIAN 159 160endchoice 161 162choice 163 prompt "CPU selection" 164 default CPU_MIPS32_R2 165 166config CPU_MIPS32_R1 167 bool "MIPS32 Release 1" 168 depends on SUPPORTS_CPU_MIPS32_R1 169 select 32BIT 170 help 171 Choose this option to build an U-Boot for release 1 through 5 of the 172 MIPS32 architecture. 173 174config CPU_MIPS32_R2 175 bool "MIPS32 Release 2" 176 depends on SUPPORTS_CPU_MIPS32_R2 177 select 32BIT 178 help 179 Choose this option to build an U-Boot for release 2 through 5 of the 180 MIPS32 architecture. 181 182config CPU_MIPS32_R6 183 bool "MIPS32 Release 6" 184 depends on SUPPORTS_CPU_MIPS32_R6 185 select 32BIT 186 help 187 Choose this option to build an U-Boot for release 6 or later of the 188 MIPS32 architecture. 189 190config CPU_MIPS64_R1 191 bool "MIPS64 Release 1" 192 depends on SUPPORTS_CPU_MIPS64_R1 193 select 64BIT 194 help 195 Choose this option to build a kernel for release 1 through 5 of the 196 MIPS64 architecture. 197 198config CPU_MIPS64_R2 199 bool "MIPS64 Release 2" 200 depends on SUPPORTS_CPU_MIPS64_R2 201 select 64BIT 202 help 203 Choose this option to build a kernel for release 2 through 5 of the 204 MIPS64 architecture. 205 206config CPU_MIPS64_R6 207 bool "MIPS64 Release 6" 208 depends on SUPPORTS_CPU_MIPS64_R6 209 select 64BIT 210 help 211 Choose this option to build a kernel for release 6 or later of the 212 MIPS64 architecture. 213 214endchoice 215 216menu "General setup" 217 218config ROM_EXCEPTION_VECTORS 219 bool "Build U-Boot image with exception vectors" 220 help 221 Enable this to include exception vectors in the U-Boot image. This is 222 required if the U-Boot entry point is equal to the address of the 223 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 224 U-Boot booted from parallel NOR flash). 225 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 226 In that case the image size will be reduced by 0x500 bytes. 227 228config MIPS_CM_BASE 229 hex "MIPS CM GCR Base Address" 230 depends on MIPS_CM 231 default 0x16100000 if TARGET_BOSTON 232 default 0x1fbf8000 233 help 234 The physical base address at which to map the MIPS Coherence Manager 235 Global Configuration Registers (GCRs). This should be set such that 236 the GCRs occupy a region of the physical address space which is 237 otherwise unused, or at minimum that software doesn't need to access. 238 239config MIPS_CACHE_INDEX_BASE 240 hex "Index base address for cache initialisation" 241 default 0x80000000 if CPU_MIPS32 242 default 0xffffffff80000000 if CPU_MIPS64 243 help 244 This is the base address for a memory block, which is used for 245 initialising the cache lines. This is also the base address of a memory 246 block which is used for loading and filling cache lines when 247 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 248 Normally this is CKSEG0. If the MIPS system needs to move this block 249 to some SRAM or ScratchPad RAM, adapt this option accordingly. 250 251endmenu 252 253menu "OS boot interface" 254 255config MIPS_BOOT_CMDLINE_LEGACY 256 bool "Hand over legacy command line to Linux kernel" 257 default y 258 help 259 Enable this option if you want U-Boot to hand over the Yamon-style 260 command line to the kernel. All bootargs will be prepared as argc/argv 261 compatible list. The argument count (argc) is stored in register $a0. 262 The address of the argument list (argv) is stored in register $a1. 263 264config MIPS_BOOT_ENV_LEGACY 265 bool "Hand over legacy environment to Linux kernel" 266 default y 267 help 268 Enable this option if you want U-Boot to hand over the Yamon-style 269 environment to the kernel. Information like memory size, initrd 270 address and size will be prepared as zero-terminated key/value list. 271 The address of the environment is stored in register $a2. 272 273config MIPS_BOOT_FDT 274 bool "Hand over a flattened device tree to Linux kernel" 275 default n 276 help 277 Enable this option if you want U-Boot to hand over a flattened 278 device tree to the kernel. According to UHI register $a0 will be set 279 to -2 and the FDT address is stored in $a1. 280 281endmenu 282 283config SUPPORTS_BIG_ENDIAN 284 bool 285 286config SUPPORTS_LITTLE_ENDIAN 287 bool 288 289config SUPPORTS_CPU_MIPS32_R1 290 bool 291 292config SUPPORTS_CPU_MIPS32_R2 293 bool 294 295config SUPPORTS_CPU_MIPS32_R6 296 bool 297 298config SUPPORTS_CPU_MIPS64_R1 299 bool 300 301config SUPPORTS_CPU_MIPS64_R2 302 bool 303 304config SUPPORTS_CPU_MIPS64_R6 305 bool 306 307config CPU_MIPS32 308 bool 309 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 310 311config CPU_MIPS64 312 bool 313 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 314 315config MIPS_TUNE_4KC 316 bool 317 318config MIPS_TUNE_14KC 319 bool 320 321config MIPS_TUNE_24KC 322 bool 323 324config MIPS_TUNE_34KC 325 bool 326 327config MIPS_TUNE_74KC 328 bool 329 330config 32BIT 331 bool 332 333config 64BIT 334 bool 335 336config SWAP_IO_SPACE 337 bool 338 339config SYS_MIPS_CACHE_INIT_RAM_LOAD 340 bool 341 342config MIPS_INIT_STACK_IN_SRAM 343 bool 344 default n 345 help 346 Select this if the initial stack frame could be setup in SRAM. 347 Normally the initial stack frame is set up in DRAM which is often 348 only available after lowlevel_init. With this option the initial 349 stack frame and the early C environment is set up before 350 lowlevel_init. Thus lowlevel_init does not need to be implemented 351 in assembler. 352 353config SYS_DCACHE_SIZE 354 int 355 default 0 356 help 357 The total size of the L1 Dcache, if known at compile time. 358 359config SYS_DCACHE_LINE_SIZE 360 int 361 default 0 362 help 363 The size of L1 Dcache lines, if known at compile time. 364 365config SYS_ICACHE_SIZE 366 int 367 default 0 368 help 369 The total size of the L1 ICache, if known at compile time. 370 371config SYS_ICACHE_LINE_SIZE 372 int 373 default 0 374 help 375 The size of L1 Icache lines, if known at compile time. 376 377config SYS_CACHE_SIZE_AUTO 378 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 379 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 380 help 381 Select this (or let it be auto-selected by not defining any cache 382 sizes) in order to allow U-Boot to automatically detect the sizes 383 of caches at runtime. This has a small cost in code size & runtime 384 so if you know the cache configuration for your system at compile 385 time it would be beneficial to configure it. 386 387config MIPS_L1_CACHE_SHIFT_4 388 bool 389 390config MIPS_L1_CACHE_SHIFT_5 391 bool 392 393config MIPS_L1_CACHE_SHIFT_6 394 bool 395 396config MIPS_L1_CACHE_SHIFT_7 397 bool 398 399config MIPS_L1_CACHE_SHIFT 400 int 401 default "7" if MIPS_L1_CACHE_SHIFT_7 402 default "6" if MIPS_L1_CACHE_SHIFT_6 403 default "5" if MIPS_L1_CACHE_SHIFT_5 404 default "4" if MIPS_L1_CACHE_SHIFT_4 405 default "5" 406 407config MIPS_L2_CACHE 408 bool 409 help 410 Select this if your system includes an L2 cache and you want U-Boot 411 to initialise & maintain it. 412 413config DYNAMIC_IO_PORT_BASE 414 bool 415 416config MIPS_CM 417 bool 418 help 419 Select this if your system contains a MIPS Coherence Manager and you 420 wish U-Boot to configure it or make use of it to retrieve system 421 information such as cache configuration. 422 423config MIPS_INSERT_BOOT_CONFIG 424 bool 425 default n 426 help 427 Enable this to insert some board-specific boot configuration in 428 the U-Boot binary at offset 0x10. 429 430config MIPS_BOOT_CONFIG_WORD0 431 hex 432 depends on MIPS_INSERT_BOOT_CONFIG 433 default 0x420 if TARGET_MALTA 434 default 0x0 435 help 436 Value which is inserted as boot config word 0. 437 438config MIPS_BOOT_CONFIG_WORD1 439 hex 440 depends on MIPS_INSERT_BOOT_CONFIG 441 default 0x0 442 help 443 Value which is inserted as boot config word 1. 444 445endif 446 447endmenu 448