1dd84058dSMasahiro Yamadamenu "MIPS architecture" 2dd84058dSMasahiro Yamada depends on MIPS 3dd84058dSMasahiro Yamada 4dd84058dSMasahiro Yamadaconfig SYS_ARCH 5dd84058dSMasahiro Yamada default "mips" 6dd84058dSMasahiro Yamada 7b9863b6dSDaniel Schwierzeckconfig SYS_CPU 820286cdfSPaul Burton default "mips32" if CPU_MIPS32 920286cdfSPaul Burton default "mips64" if CPU_MIPS64 10b9863b6dSDaniel Schwierzeck 11dd84058dSMasahiro Yamadachoice 12dd84058dSMasahiro Yamada prompt "Target select" 13a26cd049SJoe Hershberger optional 14dd84058dSMasahiro Yamada 15dd84058dSMasahiro Yamadaconfig TARGET_QEMU_MIPS 16dd84058dSMasahiro Yamada bool "Support qemu-mips" 170e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 180e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 1902611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 2002611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 21aa45f75eSDaniel Schwierzeck select SUPPORTS_CPU_MIPS64_R1 22aa45f75eSDaniel Schwierzeck select SUPPORTS_CPU_MIPS64_R2 23dd84058dSMasahiro Yamada 24dd84058dSMasahiro Yamadaconfig TARGET_MALTA 25dd84058dSMasahiro Yamada bool "Support malta" 266242aa13SPaul Burton select DM 276242aa13SPaul Burton select DM_SERIAL 2805e34255SPaul Burton select DYNAMIC_IO_PORT_BASE 296242aa13SPaul Burton select OF_CONTROL 306242aa13SPaul Burton select OF_ISA_BUS 310e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 320e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 3302611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 3402611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 3540ba13c9SPaul Burton select SUPPORTS_CPU_MIPS32_R6 360f832b9cSPaul Burton select SUPPORTS_CPU_MIPS64_R1 370f832b9cSPaul Burton select SUPPORTS_CPU_MIPS64_R2 380f832b9cSPaul Burton select SUPPORTS_CPU_MIPS64_R6 399d638eeaSDaniel Schwierzeck select SWAP_IO_SPACE 40f53830e7SDaniel Schwierzeck select MIPS_L1_CACHE_SHIFT_6 41dd84058dSMasahiro Yamada 42dd84058dSMasahiro Yamadaconfig TARGET_VCT 43dd84058dSMasahiro Yamada bool "Support vct" 440e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 4502611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 4602611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 47dd7c7200SPaul Burton select SYS_MIPS_CACHE_INIT_RAM_LOAD 48dd84058dSMasahiro Yamada 49dd84058dSMasahiro Yamadaconfig TARGET_DBAU1X00 50dd84058dSMasahiro Yamada bool "Support dbau1x00" 510e1dc345SDaniel Schwierzeck select SUPPORTS_BIG_ENDIAN 520e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 5302611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 5402611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 55dd7c7200SPaul Burton select SYS_MIPS_CACHE_INIT_RAM_LOAD 560315a289SDaniel Schwierzeck select MIPS_TUNE_4KC 57dd84058dSMasahiro Yamada 58dd84058dSMasahiro Yamadaconfig TARGET_PB1X00 59dd84058dSMasahiro Yamada bool "Support pb1x00" 600e1dc345SDaniel Schwierzeck select SUPPORTS_LITTLE_ENDIAN 6102611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R1 6202611cbbSDaniel Schwierzeck select SUPPORTS_CPU_MIPS32_R2 63dd7c7200SPaul Burton select SYS_MIPS_CACHE_INIT_RAM_LOAD 640315a289SDaniel Schwierzeck select MIPS_TUNE_4KC 65dd84058dSMasahiro Yamada 661d3d0f1fSWills Wangconfig ARCH_ATH79 671d3d0f1fSWills Wang bool "Support QCA/Atheros ath79" 681d3d0f1fSWills Wang select OF_CONTROL 691d3d0f1fSWills Wang select DM 701d3d0f1fSWills Wang 7132c1a6eeSPurna Chandra Mandalconfig MACH_PIC32 7232c1a6eeSPurna Chandra Mandal bool "Support Microchip PIC32" 7332c1a6eeSPurna Chandra Mandal select OF_CONTROL 7432c1a6eeSPurna Chandra Mandal select DM 7532c1a6eeSPurna Chandra Mandal 76*ebf2b9e3SZubair Lutfullah Kakakhelconfig TARGET_XILFPGA 77*ebf2b9e3SZubair Lutfullah Kakakhel bool "Support Imagination Xilfpga" 78*ebf2b9e3SZubair Lutfullah Kakakhel select OF_CONTROL 79*ebf2b9e3SZubair Lutfullah Kakakhel select DM 80*ebf2b9e3SZubair Lutfullah Kakakhel select DM_SERIAL 81*ebf2b9e3SZubair Lutfullah Kakakhel select DM_GPIO 82*ebf2b9e3SZubair Lutfullah Kakakhel select DM_ETH 83*ebf2b9e3SZubair Lutfullah Kakakhel select SUPPORTS_LITTLE_ENDIAN 84*ebf2b9e3SZubair Lutfullah Kakakhel select SUPPORTS_CPU_MIPS32_R1 85*ebf2b9e3SZubair Lutfullah Kakakhel select SUPPORTS_CPU_MIPS32_R2 86*ebf2b9e3SZubair Lutfullah Kakakhel select MIPS_L1_CACHE_SHIFT_4 87*ebf2b9e3SZubair Lutfullah Kakakhel help 88*ebf2b9e3SZubair Lutfullah Kakakhel This supports IMGTEC MIPSfpga platform 89*ebf2b9e3SZubair Lutfullah Kakakhel 90dd84058dSMasahiro Yamadaendchoice 91dd84058dSMasahiro Yamada 92dd84058dSMasahiro Yamadasource "board/dbau1x00/Kconfig" 93dd84058dSMasahiro Yamadasource "board/imgtec/malta/Kconfig" 94*ebf2b9e3SZubair Lutfullah Kakakhelsource "board/imgtec/xilfpga/Kconfig" 95dd84058dSMasahiro Yamadasource "board/micronas/vct/Kconfig" 96dd84058dSMasahiro Yamadasource "board/pb1x00/Kconfig" 97dd84058dSMasahiro Yamadasource "board/qemu-mips/Kconfig" 981d3d0f1fSWills Wangsource "arch/mips/mach-ath79/Kconfig" 9932c1a6eeSPurna Chandra Mandalsource "arch/mips/mach-pic32/Kconfig" 100dd84058dSMasahiro Yamada 1010e1dc345SDaniel Schwierzeckif MIPS 1020e1dc345SDaniel Schwierzeck 1030e1dc345SDaniel Schwierzeckchoice 1040e1dc345SDaniel Schwierzeck prompt "Endianness selection" 1050e1dc345SDaniel Schwierzeck help 1060e1dc345SDaniel Schwierzeck Some MIPS boards can be configured for either little or big endian 1070e1dc345SDaniel Schwierzeck byte order. These modes require different U-Boot images. In general there 1080e1dc345SDaniel Schwierzeck is one preferred byteorder for a particular system but some systems are 1090e1dc345SDaniel Schwierzeck just as commonly used in the one or the other endianness. 1100e1dc345SDaniel Schwierzeck 1110e1dc345SDaniel Schwierzeckconfig SYS_BIG_ENDIAN 1120e1dc345SDaniel Schwierzeck bool "Big endian" 1130e1dc345SDaniel Schwierzeck depends on SUPPORTS_BIG_ENDIAN 1140e1dc345SDaniel Schwierzeck 1150e1dc345SDaniel Schwierzeckconfig SYS_LITTLE_ENDIAN 1160e1dc345SDaniel Schwierzeck bool "Little endian" 1170e1dc345SDaniel Schwierzeck depends on SUPPORTS_LITTLE_ENDIAN 1180e1dc345SDaniel Schwierzeck 1190e1dc345SDaniel Schwierzeckendchoice 1200e1dc345SDaniel Schwierzeck 12102611cbbSDaniel Schwierzeckchoice 12202611cbbSDaniel Schwierzeck prompt "CPU selection" 12302611cbbSDaniel Schwierzeck default CPU_MIPS32_R2 12402611cbbSDaniel Schwierzeck 12502611cbbSDaniel Schwierzeckconfig CPU_MIPS32_R1 12602611cbbSDaniel Schwierzeck bool "MIPS32 Release 1" 12702611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS32_R1 12802611cbbSDaniel Schwierzeck select 32BIT 12902611cbbSDaniel Schwierzeck help 130c52ebea1SPaul Burton Choose this option to build an U-Boot for release 1 through 5 of the 13102611cbbSDaniel Schwierzeck MIPS32 architecture. 13202611cbbSDaniel Schwierzeck 13302611cbbSDaniel Schwierzeckconfig CPU_MIPS32_R2 13402611cbbSDaniel Schwierzeck bool "MIPS32 Release 2" 13502611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS32_R2 13602611cbbSDaniel Schwierzeck select 32BIT 13702611cbbSDaniel Schwierzeck help 138c52ebea1SPaul Burton Choose this option to build an U-Boot for release 2 through 5 of the 139c52ebea1SPaul Burton MIPS32 architecture. 140c52ebea1SPaul Burton 141c52ebea1SPaul Burtonconfig CPU_MIPS32_R6 142c52ebea1SPaul Burton bool "MIPS32 Release 6" 143c52ebea1SPaul Burton depends on SUPPORTS_CPU_MIPS32_R6 144c52ebea1SPaul Burton select 32BIT 145c52ebea1SPaul Burton help 146c52ebea1SPaul Burton Choose this option to build an U-Boot for release 6 or later of the 14702611cbbSDaniel Schwierzeck MIPS32 architecture. 14802611cbbSDaniel Schwierzeck 14902611cbbSDaniel Schwierzeckconfig CPU_MIPS64_R1 15002611cbbSDaniel Schwierzeck bool "MIPS64 Release 1" 15102611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS64_R1 15202611cbbSDaniel Schwierzeck select 64BIT 15302611cbbSDaniel Schwierzeck help 154c52ebea1SPaul Burton Choose this option to build a kernel for release 1 through 5 of the 15502611cbbSDaniel Schwierzeck MIPS64 architecture. 15602611cbbSDaniel Schwierzeck 15702611cbbSDaniel Schwierzeckconfig CPU_MIPS64_R2 15802611cbbSDaniel Schwierzeck bool "MIPS64 Release 2" 15902611cbbSDaniel Schwierzeck depends on SUPPORTS_CPU_MIPS64_R2 16002611cbbSDaniel Schwierzeck select 64BIT 16102611cbbSDaniel Schwierzeck help 162c52ebea1SPaul Burton Choose this option to build a kernel for release 2 through 5 of the 163c52ebea1SPaul Burton MIPS64 architecture. 164c52ebea1SPaul Burton 165c52ebea1SPaul Burtonconfig CPU_MIPS64_R6 166c52ebea1SPaul Burton bool "MIPS64 Release 6" 167c52ebea1SPaul Burton depends on SUPPORTS_CPU_MIPS64_R6 168c52ebea1SPaul Burton select 64BIT 169c52ebea1SPaul Burton help 170c52ebea1SPaul Burton Choose this option to build a kernel for release 6 or later of the 17102611cbbSDaniel Schwierzeck MIPS64 architecture. 17202611cbbSDaniel Schwierzeck 17302611cbbSDaniel Schwierzeckendchoice 17402611cbbSDaniel Schwierzeck 17525fc664fSDaniel Schwierzeckmenu "OS boot interface" 17625fc664fSDaniel Schwierzeck 17725fc664fSDaniel Schwierzeckconfig MIPS_BOOT_CMDLINE_LEGACY 17825fc664fSDaniel Schwierzeck bool "Hand over legacy command line to Linux kernel" 17925fc664fSDaniel Schwierzeck default y 18025fc664fSDaniel Schwierzeck help 18125fc664fSDaniel Schwierzeck Enable this option if you want U-Boot to hand over the Yamon-style 18225fc664fSDaniel Schwierzeck command line to the kernel. All bootargs will be prepared as argc/argv 18325fc664fSDaniel Schwierzeck compatible list. The argument count (argc) is stored in register $a0. 18425fc664fSDaniel Schwierzeck The address of the argument list (argv) is stored in register $a1. 18525fc664fSDaniel Schwierzeck 186ca65e585SDaniel Schwierzeckconfig MIPS_BOOT_ENV_LEGACY 187ca65e585SDaniel Schwierzeck bool "Hand over legacy environment to Linux kernel" 188ca65e585SDaniel Schwierzeck default y 189ca65e585SDaniel Schwierzeck help 190ca65e585SDaniel Schwierzeck Enable this option if you want U-Boot to hand over the Yamon-style 191ca65e585SDaniel Schwierzeck environment to the kernel. Information like memory size, initrd 192ca65e585SDaniel Schwierzeck address and size will be prepared as zero-terminated key/value list. 1931cc0a9f4SRobert P. J. Day The address of the environment is stored in register $a2. 194ca65e585SDaniel Schwierzeck 1955002d8ccSDaniel Schwierzeckconfig MIPS_BOOT_FDT 19690b1c9faSDaniel Schwierzeck bool "Hand over a flattened device tree to Linux kernel" 1975002d8ccSDaniel Schwierzeck default n 1985002d8ccSDaniel Schwierzeck help 1995002d8ccSDaniel Schwierzeck Enable this option if you want U-Boot to hand over a flattened 20090b1c9faSDaniel Schwierzeck device tree to the kernel. According to UHI register $a0 will be set 20190b1c9faSDaniel Schwierzeck to -2 and the FDT address is stored in $a1. 2025002d8ccSDaniel Schwierzeck 20325fc664fSDaniel Schwierzeckendmenu 20425fc664fSDaniel Schwierzeck 2050e1dc345SDaniel Schwierzeckconfig SUPPORTS_BIG_ENDIAN 2060e1dc345SDaniel Schwierzeck bool 2070e1dc345SDaniel Schwierzeck 2080e1dc345SDaniel Schwierzeckconfig SUPPORTS_LITTLE_ENDIAN 2090e1dc345SDaniel Schwierzeck bool 2100e1dc345SDaniel Schwierzeck 21102611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS32_R1 21202611cbbSDaniel Schwierzeck bool 21302611cbbSDaniel Schwierzeck 21402611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS32_R2 21502611cbbSDaniel Schwierzeck bool 21602611cbbSDaniel Schwierzeck 217c52ebea1SPaul Burtonconfig SUPPORTS_CPU_MIPS32_R6 218c52ebea1SPaul Burton bool 219c52ebea1SPaul Burton 22002611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS64_R1 22102611cbbSDaniel Schwierzeck bool 22202611cbbSDaniel Schwierzeck 22302611cbbSDaniel Schwierzeckconfig SUPPORTS_CPU_MIPS64_R2 22402611cbbSDaniel Schwierzeck bool 22502611cbbSDaniel Schwierzeck 226c52ebea1SPaul Burtonconfig SUPPORTS_CPU_MIPS64_R6 227c52ebea1SPaul Burton bool 228c52ebea1SPaul Burton 229c57dafb5SDaniel Schwierzeckconfig CPU_MIPS32 230c57dafb5SDaniel Schwierzeck bool 231c52ebea1SPaul Burton default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 232c57dafb5SDaniel Schwierzeck 233c57dafb5SDaniel Schwierzeckconfig CPU_MIPS64 234c57dafb5SDaniel Schwierzeck bool 235c52ebea1SPaul Burton default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 236c57dafb5SDaniel Schwierzeck 2370315a289SDaniel Schwierzeckconfig MIPS_TUNE_4KC 2380315a289SDaniel Schwierzeck bool 2390315a289SDaniel Schwierzeck 2400315a289SDaniel Schwierzeckconfig MIPS_TUNE_14KC 2410315a289SDaniel Schwierzeck bool 2420315a289SDaniel Schwierzeck 2430315a289SDaniel Schwierzeckconfig MIPS_TUNE_24KC 2440315a289SDaniel Schwierzeck bool 2450315a289SDaniel Schwierzeck 2465f9cc363SDaniel Schwierzeckconfig MIPS_TUNE_34KC 2475f9cc363SDaniel Schwierzeck bool 2485f9cc363SDaniel Schwierzeck 2490a0a958bSMarek Vasutconfig MIPS_TUNE_74KC 2500a0a958bSMarek Vasut bool 2510a0a958bSMarek Vasut 25202611cbbSDaniel Schwierzeckconfig 32BIT 25302611cbbSDaniel Schwierzeck bool 25402611cbbSDaniel Schwierzeck 25502611cbbSDaniel Schwierzeckconfig 64BIT 25602611cbbSDaniel Schwierzeck bool 25702611cbbSDaniel Schwierzeck 2589d638eeaSDaniel Schwierzeckconfig SWAP_IO_SPACE 2599d638eeaSDaniel Schwierzeck bool 2609d638eeaSDaniel Schwierzeck 261dd7c7200SPaul Burtonconfig SYS_MIPS_CACHE_INIT_RAM_LOAD 262dd7c7200SPaul Burton bool 263dd7c7200SPaul Burton 264ace3be4fSPaul Burtonconfig SYS_DCACHE_SIZE 265ace3be4fSPaul Burton int 266ace3be4fSPaul Burton default 0 267ace3be4fSPaul Burton help 268ace3be4fSPaul Burton The total size of the L1 Dcache, if known at compile time. 269ace3be4fSPaul Burton 27037228621SPaul Burtonconfig SYS_DCACHE_LINE_SIZE 2714b7b0a0fSPaul Burton int 27237228621SPaul Burton default 0 27337228621SPaul Burton help 27437228621SPaul Burton The size of L1 Dcache lines, if known at compile time. 27537228621SPaul Burton 276ace3be4fSPaul Burtonconfig SYS_ICACHE_SIZE 277ace3be4fSPaul Burton int 278ace3be4fSPaul Burton default 0 279ace3be4fSPaul Burton help 280ace3be4fSPaul Burton The total size of the L1 ICache, if known at compile time. 281ace3be4fSPaul Burton 28237228621SPaul Burtonconfig SYS_ICACHE_LINE_SIZE 283ace3be4fSPaul Burton int 284ace3be4fSPaul Burton default 0 285ace3be4fSPaul Burton help 28637228621SPaul Burton The size of L1 Icache lines, if known at compile time. 287ace3be4fSPaul Burton 288ace3be4fSPaul Burtonconfig SYS_CACHE_SIZE_AUTO 289ace3be4fSPaul Burton def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 29037228621SPaul Burton SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 291ace3be4fSPaul Burton help 292ace3be4fSPaul Burton Select this (or let it be auto-selected by not defining any cache 293ace3be4fSPaul Burton sizes) in order to allow U-Boot to automatically detect the sizes 294ace3be4fSPaul Burton of caches at runtime. This has a small cost in code size & runtime 295ace3be4fSPaul Burton so if you know the cache configuration for your system at compile 296ace3be4fSPaul Burton time it would be beneficial to configure it. 297ace3be4fSPaul Burton 298f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_4 299f53830e7SDaniel Schwierzeck bool 300f53830e7SDaniel Schwierzeck 301f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_5 302f53830e7SDaniel Schwierzeck bool 303f53830e7SDaniel Schwierzeck 304f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_6 305f53830e7SDaniel Schwierzeck bool 306f53830e7SDaniel Schwierzeck 307f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT_7 308f53830e7SDaniel Schwierzeck bool 309f53830e7SDaniel Schwierzeck 310f53830e7SDaniel Schwierzeckconfig MIPS_L1_CACHE_SHIFT 311f53830e7SDaniel Schwierzeck int 312f53830e7SDaniel Schwierzeck default "7" if MIPS_L1_CACHE_SHIFT_7 313f53830e7SDaniel Schwierzeck default "6" if MIPS_L1_CACHE_SHIFT_6 314f53830e7SDaniel Schwierzeck default "5" if MIPS_L1_CACHE_SHIFT_5 315f53830e7SDaniel Schwierzeck default "4" if MIPS_L1_CACHE_SHIFT_4 316f53830e7SDaniel Schwierzeck default "5" 317f53830e7SDaniel Schwierzeck 31805e34255SPaul Burtonconfig DYNAMIC_IO_PORT_BASE 31905e34255SPaul Burton bool 32005e34255SPaul Burton 3210e1dc345SDaniel Schwierzeckendif 3220e1dc345SDaniel Schwierzeck 323dd84058dSMasahiro Yamadaendmenu 324