1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 3 #ifndef _ABI_MACH_ASPEED_AST2400_RESET_H_ 4 #define _ABI_MACH_ASPEED_AST2400_RESET_H_ 5 6 /* 7 * The values are intentionally layed out as flags in 8 * WDT reset parameter. 9 */ 10 #define ASPEED_RESET_RESERVED31 (31) 11 #define ASPEED_RESET_RESERVED30 (30) 12 #define ASPEED_RESET_RESERVED29 (29) 13 #define ASPEED_RESET_RESERVED28 (28) 14 #define ASPEED_RESET_RESERVED27 (27) 15 #define ASPEED_RESET_RESERVED26 (26) 16 #define ASPEED_RESET_XDMA (25) 17 #define ASPEED_RESET_MCTP (24) 18 #define ASPEED_RESET_ADC (23) 19 #define ASPEED_RESET_JTAG_MASTER (22) 20 #define ASPEED_RESET_RESERVED21 (21) 21 #define ASPEED_RESET_RESERVED20 (20) 22 #define ASPEED_RESET_RESERVED19 (19) 23 #define ASPEED_RESET_MIC (18) 24 #define ASPEED_RESET_RESERVED17 (17) 25 #define ASEPPD_RESET_SDIO (16) 26 #define ASPEED_RESET_UHCI (15) 27 #define ASPEED_RESET_EHCI_P1 (14) 28 #define ASPEED_RESET_CRT (13) 29 #define ASPEED_RESET_MAC2 (12) 30 #define ASPEED_RESET_MAC1 (11) 31 #define ASPEED_RESET_PECI (10) 32 #define ASPEED_RESET_PWM (9) 33 #define ASPEED_RESET_PCI_VGA (8) 34 #define ASPEED_RESET_2D (7) 35 #define ASPEED_RESET_VIDEO (6) 36 #define ASPEED_RESET_LPC (5) 37 #define ASPEED_RESET_HACE (4) 38 #define ASPEED_RESET_EHCI_P2 (3) 39 #define ASPEED_RESET_I2C (2) 40 #define ASPEED_RESET_AHB (1) 41 #define ASPEED_RESET_SDRAM (0) 42 43 #endif /* _ABI_MACH_ASPEED_AST2400_RESET_H_ */ 44