1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/processor.h> 29 #include <asm/immap.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ 34 int get_clocks (void) 35 { 36 #if defined(CONFIG_M5208) 37 volatile pll_t *pll = (pll_t *) MMAP_PLL; 38 39 pll->odr = CONFIG_SYS_PLL_ODR; 40 pll->fdr = CONFIG_SYS_PLL_FDR; 41 #endif 42 43 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); 45 unsigned long pllcr; 46 47 #ifndef CONFIG_SYS_PLL_BYPASS 48 49 #ifdef CONFIG_M5249 50 /* Setup the PLL to run at the specified speed */ 51 #ifdef CONFIG_SYS_FAST_CLK 52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ 53 #else 54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ 55 #endif 56 #endif /* CONFIG_M5249 */ 57 58 #ifdef CONFIG_M5253 59 pllcr = CONFIG_SYS_PLLCR; 60 #endif /* CONFIG_M5253 */ 61 62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ 63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ 64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ 65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ 66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ 67 udelay(0x20); /* Wait for a lock ... */ 68 #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ 69 70 #endif /* CONFIG_M5249 || CONFIG_M5253 */ 71 72 #if defined(CONFIG_M5275) 73 volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); 74 75 /* Setup PLL */ 76 pll->syncr = 0x01080000; 77 while (!(pll->synsr & FMPLL_SYNSR_LOCK)) 78 ; 79 pll->syncr = 0x01000000; 80 while (!(pll->synsr & FMPLL_SYNSR_LOCK)) 81 ; 82 #endif 83 84 gd->cpu_clk = CONFIG_SYS_CLK; 85 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ 86 defined(CONFIG_M5271) || defined(CONFIG_M5275) 87 gd->bus_clk = gd->cpu_clk / 2; 88 #else 89 gd->bus_clk = gd->cpu_clk; 90 #endif 91 92 #ifdef CONFIG_FSL_I2C 93 gd->i2c1_clk = gd->bus_clk; 94 #ifdef CONFIG_SYS_I2C2_OFFSET 95 gd->i2c2_clk = gd->bus_clk; 96 #endif 97 #endif 98 99 return (0); 100 } 101