1 /* 2 * (C) Copyright 2003 3 * Josef Baumgartner <josef.baumgartner@telex.de> 4 * 5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 6 * Hayden Fraser (Hayden.Fraser@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <asm/processor.h> 29 #include <asm/immap.h> 30 #include <asm/io.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ 35 int get_clocks (void) 36 { 37 #if defined(CONFIG_M5208) 38 pll_t *pll = (pll_t *) MMAP_PLL; 39 40 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); 41 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); 42 #endif 43 44 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 45 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); 46 unsigned long pllcr; 47 48 #ifndef CONFIG_SYS_PLL_BYPASS 49 50 #ifdef CONFIG_M5249 51 /* Setup the PLL to run at the specified speed */ 52 #ifdef CONFIG_SYS_FAST_CLK 53 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ 54 #else 55 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ 56 #endif 57 #endif /* CONFIG_M5249 */ 58 59 #ifdef CONFIG_M5253 60 pllcr = CONFIG_SYS_PLLCR; 61 #endif /* CONFIG_M5253 */ 62 63 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ 64 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ 65 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ 66 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ 67 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ 68 udelay(0x20); /* Wait for a lock ... */ 69 #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ 70 71 #endif /* CONFIG_M5249 || CONFIG_M5253 */ 72 73 #if defined(CONFIG_M5275) 74 pll_t *pll = (pll_t *)(MMAP_PLL); 75 76 /* Setup PLL */ 77 out_be32(&pll->syncr, 0x01080000); 78 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 79 ; 80 out_be32(&pll->syncr, 0x01000000); 81 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 82 ; 83 #endif 84 85 gd->cpu_clk = CONFIG_SYS_CLK; 86 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ 87 defined(CONFIG_M5271) || defined(CONFIG_M5275) 88 gd->bus_clk = gd->cpu_clk / 2; 89 #else 90 gd->bus_clk = gd->cpu_clk; 91 #endif 92 93 #ifdef CONFIG_FSL_I2C 94 gd->arch.i2c1_clk = gd->bus_clk; 95 #ifdef CONFIG_SYS_I2C2_OFFSET 96 gd->arch.i2c2_clk = gd->bus_clk; 97 #endif 98 #endif 99 100 return (0); 101 } 102