12514c2d0SPatrick Delaunayif ARCH_STM32MP 22514c2d0SPatrick Delaunay 32514c2d0SPatrick Delaunayconfig SPL 42514c2d0SPatrick Delaunay select SPL_BOARD_INIT 52514c2d0SPatrick Delaunay select SPL_CLK 62514c2d0SPatrick Delaunay select SPL_DM 72514c2d0SPatrick Delaunay select SPL_DM_SEQ_ALIAS 82514c2d0SPatrick Delaunay select SPL_FRAMEWORK 92514c2d0SPatrick Delaunay select SPL_GPIO_SUPPORT 102514c2d0SPatrick Delaunay select SPL_LIBCOMMON_SUPPORT 112514c2d0SPatrick Delaunay select SPL_LIBGENERIC_SUPPORT 122514c2d0SPatrick Delaunay select SPL_OF_CONTROL 132514c2d0SPatrick Delaunay select SPL_OF_TRANSLATE 142514c2d0SPatrick Delaunay select SPL_PINCTRL 152514c2d0SPatrick Delaunay select SPL_REGMAP 162514c2d0SPatrick Delaunay select SPL_RESET_SUPPORT 172514c2d0SPatrick Delaunay select SPL_SERIAL_SUPPORT 182514c2d0SPatrick Delaunay select SPL_SYSCON 192514c2d0SPatrick Delaunay imply SPL_LIBDISK_SUPPORT 202514c2d0SPatrick Delaunay 212514c2d0SPatrick Delaunayconfig SYS_SOC 222514c2d0SPatrick Delaunay default "stm32mp" 232514c2d0SPatrick Delaunay 242514c2d0SPatrick Delaunayconfig TARGET_STM32MP1 252514c2d0SPatrick Delaunay bool "Support stm32mp1xx" 262514c2d0SPatrick Delaunay select CPU_V7 272514c2d0SPatrick Delaunay select PINCTRL_STM32 282514c2d0SPatrick Delaunay select STM32_RESET 292514c2d0SPatrick Delaunay help 302514c2d0SPatrick Delaunay target STMicroelectronics SOC STM32MP1 family 312514c2d0SPatrick Delaunay STMicroelectronics MPU with core ARMv7 322514c2d0SPatrick Delaunay 332514c2d0SPatrick Delaunayconfig SYS_TEXT_BASE 342514c2d0SPatrick Delaunay prompt "U-Boot base address" 352514c2d0SPatrick Delaunay default 0xC0100000 362514c2d0SPatrick Delaunay help 372514c2d0SPatrick Delaunay configure the U-Boot base address 382514c2d0SPatrick Delaunay when DDR driver is used: 392514c2d0SPatrick Delaunay DDR + 1MB (0xC0100000) 402514c2d0SPatrick Delaunay 41*f8598d98SPatrick Delaunaysource "board/st/stm32mp1/Kconfig" 42*f8598d98SPatrick Delaunay 432514c2d0SPatrick Delaunayendif 44