1*2514c2d0SPatrick Delaunayif ARCH_STM32MP 2*2514c2d0SPatrick Delaunay 3*2514c2d0SPatrick Delaunayconfig SPL 4*2514c2d0SPatrick Delaunay select SPL_BOARD_INIT 5*2514c2d0SPatrick Delaunay select SPL_CLK 6*2514c2d0SPatrick Delaunay select SPL_DM 7*2514c2d0SPatrick Delaunay select SPL_DM_SEQ_ALIAS 8*2514c2d0SPatrick Delaunay select SPL_FRAMEWORK 9*2514c2d0SPatrick Delaunay select SPL_GPIO_SUPPORT 10*2514c2d0SPatrick Delaunay select SPL_LIBCOMMON_SUPPORT 11*2514c2d0SPatrick Delaunay select SPL_LIBGENERIC_SUPPORT 12*2514c2d0SPatrick Delaunay select SPL_OF_CONTROL 13*2514c2d0SPatrick Delaunay select SPL_OF_TRANSLATE 14*2514c2d0SPatrick Delaunay select SPL_PINCTRL 15*2514c2d0SPatrick Delaunay select SPL_REGMAP 16*2514c2d0SPatrick Delaunay select SPL_RESET_SUPPORT 17*2514c2d0SPatrick Delaunay select SPL_SERIAL_SUPPORT 18*2514c2d0SPatrick Delaunay select SPL_SYSCON 19*2514c2d0SPatrick Delaunay imply SPL_LIBDISK_SUPPORT 20*2514c2d0SPatrick Delaunay 21*2514c2d0SPatrick Delaunayconfig SYS_SOC 22*2514c2d0SPatrick Delaunay default "stm32mp" 23*2514c2d0SPatrick Delaunay 24*2514c2d0SPatrick Delaunayconfig TARGET_STM32MP1 25*2514c2d0SPatrick Delaunay bool "Support stm32mp1xx" 26*2514c2d0SPatrick Delaunay select CPU_V7 27*2514c2d0SPatrick Delaunay select PINCTRL_STM32 28*2514c2d0SPatrick Delaunay select STM32_RESET 29*2514c2d0SPatrick Delaunay help 30*2514c2d0SPatrick Delaunay target STMicroelectronics SOC STM32MP1 family 31*2514c2d0SPatrick Delaunay STMicroelectronics MPU with core ARMv7 32*2514c2d0SPatrick Delaunay 33*2514c2d0SPatrick Delaunayconfig SYS_TEXT_BASE 34*2514c2d0SPatrick Delaunay prompt "U-Boot base address" 35*2514c2d0SPatrick Delaunay default 0xC0100000 36*2514c2d0SPatrick Delaunay help 37*2514c2d0SPatrick Delaunay configure the U-Boot base address 38*2514c2d0SPatrick Delaunay when DDR driver is used: 39*2514c2d0SPatrick Delaunay DDR + 1MB (0xC0100000) 40*2514c2d0SPatrick Delaunay 41*2514c2d0SPatrick Delaunayendif 42