1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #include <altera.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 #include <ns16550.h> 13 #include <watchdog.h> 14 #include <asm/arch/misc.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/reset_manager_arria10.h> 18 #include <asm/arch/sdram_arria10.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/io.h> 22 #include <asm/pl310.h> 23 24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 30 31 static struct socfpga_system_manager *sysmgr_regs = 32 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 33 #if defined(CONFIG_SPL_BUILD) 34 static struct pl310_regs *const pl310 = 35 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 36 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = 37 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; 38 39 /* 40 + * This function initializes security policies to be consistent across 41 + * all logic units in the Arria 10. 42 + * 43 + * The idea is to set all security policies to be normal, nonsecure 44 + * for all units. 45 + */ 46 void socfpga_init_security_policies(void) 47 { 48 /* Put OCRAM in non-secure */ 49 writel(0x003f0000, &noc_fw_ocram_base->region0); 50 writel(0x1, &noc_fw_ocram_base->enable); 51 52 /* Put DDR in non-secure */ 53 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); 54 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS); 55 56 /* Enable priviledged and non-priviledged access to L4 peripherals */ 57 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST); 58 59 /* Enable secure and non-secure transactions to bridges */ 60 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); 61 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); 62 63 writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); 64 } 65 66 void socfpga_sdram_remap_zero(void) 67 { 68 /* Configure the L2 controller to make SDRAM start at 0 */ 69 writel(0x1, &pl310->pl310_addr_filter_start); 70 } 71 #endif 72 73 int arch_early_init_r(void) 74 { 75 /* Add device descriptor to FPGA device table */ 76 socfpga_fpga_add(); 77 78 return 0; 79 } 80 81 /* 82 * Print CPU information 83 */ 84 #if defined(CONFIG_DISPLAY_CPUINFO) 85 int print_cpuinfo(void) 86 { 87 const u32 bsel = 88 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 89 90 puts("CPU: Altera SoCFPGA Arria 10\n"); 91 92 printf("BOOT: %s\n", bsel_str[bsel].name); 93 return 0; 94 } 95 #endif 96 97 void do_bridge_reset(int enable) 98 { 99 if (enable) 100 socfpga_reset_deassert_bridges_handoff(); 101 else 102 socfpga_bridges_reset(); 103 } 104