1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #include <altera.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 #include <ns16550.h> 13 #include <watchdog.h> 14 #include <asm/arch/misc.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/reset_manager_arria10.h> 18 #include <asm/arch/sdram_arria10.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/io.h> 22 #include <asm/pl310.h> 23 24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 30 31 #if defined(CONFIG_SPL_BUILD) 32 static struct pl310_regs *const pl310 = 33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 34 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = 35 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; 36 #endif 37 38 static struct socfpga_system_manager *sysmgr_regs = 39 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 40 41 #if defined(CONFIG_SPL_BUILD) 42 /* 43 + * This function initializes security policies to be consistent across 44 + * all logic units in the Arria 10. 45 + * 46 + * The idea is to set all security policies to be normal, nonsecure 47 + * for all units. 48 + */ 49 static void initialize_security_policies(void) 50 { 51 /* Put OCRAM in non-secure */ 52 writel(0x003f0000, &noc_fw_ocram_base->region0); 53 writel(0x1, &noc_fw_ocram_base->enable); 54 55 /* Put DDR in non-secure */ 56 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); 57 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS); 58 59 /* Enable priviledged and non-priviledged access to L4 peripherals */ 60 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST); 61 62 /* Enable secure and non-secure transactions to bridges */ 63 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); 64 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); 65 66 writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); 67 } 68 69 int arch_early_init_r(void) 70 { 71 initialize_security_policies(); 72 73 /* Configure the L2 controller to make SDRAM start at 0 */ 74 writel(0x1, &pl310->pl310_addr_filter_start); 75 76 /* assert reset to all except L4WD0 and L4TIMER0 */ 77 socfpga_per_reset_all(); 78 79 return 0; 80 } 81 #else 82 int arch_early_init_r(void) 83 { 84 return 0; 85 } 86 #endif 87 88 /* 89 * Print CPU information 90 */ 91 #if defined(CONFIG_DISPLAY_CPUINFO) 92 int print_cpuinfo(void) 93 { 94 const u32 bsel = 95 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 96 97 puts("CPU: Altera SoCFPGA Arria 10\n"); 98 99 printf("BOOT: %s\n", bsel_str[bsel].name); 100 return 0; 101 } 102 #endif 103 104 void do_bridge_reset(int enable) 105 { 106 if (enable) 107 socfpga_reset_deassert_bridges_handoff(); 108 else 109 socfpga_bridges_reset(); 110 } 111