1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #include <altera.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 #include <ns16550.h> 13 #include <watchdog.h> 14 #include <asm/arch/misc.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/reset_manager_arria10.h> 18 #include <asm/arch/sdram_arria10.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/io.h> 22 #include <asm/pl310.h> 23 24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 30 31 #if defined(CONFIG_SPL_BUILD) 32 static struct pl310_regs *const pl310 = 33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 34 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = 35 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; 36 #endif 37 38 static struct socfpga_system_manager *sysmgr_regs = 39 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 40 41 /* 42 * DesignWare Ethernet initialization 43 */ 44 #ifdef CONFIG_ETH_DESIGNWARE 45 static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode) 46 { 47 u32 reset; 48 49 if (of_reset_id == EMAC0_RESET) { 50 reset = SOCFPGA_RESET(EMAC0); 51 } else if (of_reset_id == EMAC1_RESET) { 52 reset = SOCFPGA_RESET(EMAC1); 53 } else if (of_reset_id == EMAC2_RESET) { 54 reset = SOCFPGA_RESET(EMAC2); 55 } else { 56 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 57 return; 58 } 59 60 clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], 61 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, 62 phymode); 63 64 /* Release the EMAC controller from reset */ 65 socfpga_per_reset(reset, 0); 66 } 67 68 static int socfpga_eth_reset(void) 69 { 70 /* Put all GMACs into RESET state. */ 71 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); 72 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); 73 socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1); 74 return socfpga_eth_reset_common(arria10_dwmac_reset); 75 }; 76 #else 77 static int socfpga_eth_reset(void) 78 { 79 return 0; 80 }; 81 #endif 82 83 #if defined(CONFIG_SPL_BUILD) 84 /* 85 + * This function initializes security policies to be consistent across 86 + * all logic units in the Arria 10. 87 + * 88 + * The idea is to set all security policies to be normal, nonsecure 89 + * for all units. 90 + */ 91 static void initialize_security_policies(void) 92 { 93 /* Put OCRAM in non-secure */ 94 writel(0x003f0000, &noc_fw_ocram_base->region0); 95 writel(0x1, &noc_fw_ocram_base->enable); 96 97 /* Put DDR in non-secure */ 98 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); 99 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS); 100 101 /* Enable priviledged and non-priviledged access to L4 peripherals */ 102 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST); 103 104 /* Enable secure and non-secure transactions to bridges */ 105 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); 106 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); 107 108 writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); 109 } 110 111 int arch_early_init_r(void) 112 { 113 initialize_security_policies(); 114 115 /* Configure the L2 controller to make SDRAM start at 0 */ 116 writel(0x1, &pl310->pl310_addr_filter_start); 117 118 /* assert reset to all except L4WD0 and L4TIMER0 */ 119 socfpga_per_reset_all(); 120 121 return 0; 122 } 123 #else 124 int arch_early_init_r(void) 125 { 126 return 0; 127 } 128 #endif 129 130 /* 131 * This function looking the 1st encounter UART peripheral, 132 * and then return its offset of the dedicated/shared IO pin 133 * mux. offset value (zero and above). 134 */ 135 static int find_peripheral_uart(const void *blob, 136 int child, const char *node_name) 137 { 138 int len; 139 fdt_addr_t base_addr = 0; 140 fdt_size_t size; 141 const u32 *cell; 142 u32 value, offset = 0; 143 144 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); 145 if (base_addr != FDT_ADDR_T_NONE) { 146 cell = fdt_getprop(blob, child, "pinctrl-single,pins", 147 &len); 148 if (cell != NULL) { 149 for (; len > 0; len -= (2 * sizeof(u32))) { 150 offset = fdt32_to_cpu(*cell++); 151 value = fdt32_to_cpu(*cell++); 152 /* Found UART peripheral. */ 153 if (value == PINMUX_UART) 154 return offset; 155 } 156 } 157 } 158 return -EINVAL; 159 } 160 161 /* 162 * This function looks up the 1st encounter UART peripheral, 163 * and then return its offset of the dedicated/shared IO pin 164 * mux. UART peripheral is found if the offset is not in negative 165 * value. 166 */ 167 static int is_peripheral_uart_true(const void *blob, 168 int node, const char *child_name) 169 { 170 int child, len; 171 const char *node_name; 172 173 child = fdt_first_subnode(blob, node); 174 175 if (child < 0) 176 return -EINVAL; 177 178 node_name = fdt_get_name(blob, child, &len); 179 180 while (node_name) { 181 if (!strcmp(child_name, node_name)) 182 return find_peripheral_uart(blob, child, node_name); 183 184 child = fdt_next_subnode(blob, child); 185 if (child < 0) 186 break; 187 188 node_name = fdt_get_name(blob, child, &len); 189 } 190 191 return -1; 192 } 193 194 /* 195 * This function looking the 1st encounter UART dedicated IO peripheral, 196 * and then return based address of the 1st encounter UART dedicated 197 * IO peripheral. 198 */ 199 unsigned int dedicated_uart_com_port(const void *blob) 200 { 201 int node; 202 203 node = fdtdec_next_compatible(blob, 0, 204 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); 205 if (node < 0) 206 return 0; 207 208 if (is_peripheral_uart_true(blob, node, "dedicated") >= 0) 209 return SOCFPGA_UART1_ADDRESS; 210 211 return 0; 212 } 213 214 /* 215 * This function looking the 1st encounter UART shared IO peripheral, and then 216 * return based address of the 1st encounter UART shared IO peripheral. 217 */ 218 unsigned int shared_uart_com_port(const void *blob) 219 { 220 int node, ret; 221 222 node = fdtdec_next_compatible(blob, 0, 223 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); 224 if (node < 0) 225 return 0; 226 227 ret = is_peripheral_uart_true(blob, node, "shared"); 228 229 if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 || 230 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 || 231 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3) 232 return SOCFPGA_UART0_ADDRESS; 233 else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 || 234 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 || 235 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3) 236 return SOCFPGA_UART1_ADDRESS; 237 238 return 0; 239 } 240 241 /* 242 * This function looking the 1st encounter UART peripheral, and then return 243 * base address of the 1st encounter UART peripheral. 244 */ 245 unsigned int uart_com_port(const void *blob) 246 { 247 unsigned int ret; 248 249 ret = dedicated_uart_com_port(blob); 250 251 if (ret) 252 return ret; 253 254 return shared_uart_com_port(blob); 255 } 256 257 /* 258 * Print CPU information 259 */ 260 #if defined(CONFIG_DISPLAY_CPUINFO) 261 int print_cpuinfo(void) 262 { 263 const u32 bsel = 264 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 265 266 puts("CPU: Altera SoCFPGA Arria 10\n"); 267 268 printf("BOOT: %s\n", bsel_str[bsel].name); 269 return 0; 270 } 271 #endif 272 273 #ifdef CONFIG_ARCH_MISC_INIT 274 int arch_misc_init(void) 275 { 276 return socfpga_eth_reset(); 277 } 278 #endif 279 280 void do_bridge_reset(int enable) 281 { 282 if (enable) 283 socfpga_reset_deassert_bridges_handoff(); 284 else 285 socfpga_bridges_reset(); 286 } 287