1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #include <altera.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 #include <ns16550.h> 13 #include <watchdog.h> 14 #include <asm/arch/misc.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/reset_manager_arria10.h> 18 #include <asm/arch/sdram_arria10.h> 19 #include <asm/arch/system_manager.h> 20 #include <asm/arch/nic301.h> 21 #include <asm/io.h> 22 #include <asm/pl310.h> 23 24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 26 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 29 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 30 31 static struct socfpga_system_manager *sysmgr_regs = 32 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 33 34 /* 35 * FPGA programming support for SoC FPGA Arria 10 36 */ 37 static Altera_desc altera_fpga[] = { 38 { 39 /* Family */ 40 Altera_SoCFPGA, 41 /* Interface type */ 42 fast_passive_parallel, 43 /* No limitation as additional data will be ignored */ 44 -1, 45 /* No device function table */ 46 NULL, 47 /* Base interface address specified in driver */ 48 NULL, 49 /* No cookie implementation */ 50 0 51 }, 52 }; 53 54 #if defined(CONFIG_SPL_BUILD) 55 static struct pl310_regs *const pl310 = 56 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 57 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = 58 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; 59 60 /* 61 + * This function initializes security policies to be consistent across 62 + * all logic units in the Arria 10. 63 + * 64 + * The idea is to set all security policies to be normal, nonsecure 65 + * for all units. 66 + */ 67 void socfpga_init_security_policies(void) 68 { 69 /* Put OCRAM in non-secure */ 70 writel(0x003f0000, &noc_fw_ocram_base->region0); 71 writel(0x1, &noc_fw_ocram_base->enable); 72 73 /* Put DDR in non-secure */ 74 writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); 75 writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS); 76 77 /* Enable priviledged and non-priviledged access to L4 peripherals */ 78 writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST); 79 80 /* Enable secure and non-secure transactions to bridges */ 81 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); 82 writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); 83 84 writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); 85 } 86 87 void socfpga_sdram_remap_zero(void) 88 { 89 /* Configure the L2 controller to make SDRAM start at 0 */ 90 writel(0x1, &pl310->pl310_addr_filter_start); 91 } 92 #endif 93 94 int arch_early_init_r(void) 95 { 96 /* Add device descriptor to FPGA device table */ 97 socfpga_fpga_add(&altera_fpga[0]); 98 99 return 0; 100 } 101 102 /* 103 * Print CPU information 104 */ 105 #if defined(CONFIG_DISPLAY_CPUINFO) 106 int print_cpuinfo(void) 107 { 108 const u32 bsel = 109 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 110 111 puts("CPU: Altera SoCFPGA Arria 10\n"); 112 113 printf("BOOT: %s\n", bsel_str[bsel].name); 114 return 0; 115 } 116 #endif 117 118 void do_bridge_reset(int enable) 119 { 120 if (enable) 121 socfpga_reset_deassert_bridges_handoff(); 122 else 123 socfpga_bridges_reset(); 124 } 125