1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #include <altera.h> 7 #include <common.h> 8 #include <errno.h> 9 #include <fdtdec.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 #include <ns16550.h> 13 #include <watchdog.h> 14 #include <asm/arch/misc.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/reset_manager.h> 17 #include <asm/arch/sdram_arria10.h> 18 #include <asm/arch/system_manager.h> 19 #include <asm/arch/nic301.h> 20 #include <asm/io.h> 21 #include <asm/pl310.h> 22 23 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 24 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 25 #define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 26 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 27 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 28 #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 29 30 #if defined(CONFIG_SPL_BUILD) 31 static struct pl310_regs *const pl310 = 32 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 33 static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = 34 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; 35 #endif 36 37 static struct socfpga_system_manager *sysmgr_regs = 38 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 39 40 /* 41 * DesignWare Ethernet initialization 42 */ 43 #ifdef CONFIG_ETH_DESIGNWARE 44 void dwmac_deassert_reset(const unsigned int of_reset_id, 45 const u32 phymode) 46 { 47 u32 reset; 48 49 if (of_reset_id == EMAC0_RESET) { 50 reset = SOCFPGA_RESET(EMAC0); 51 } else if (of_reset_id == EMAC1_RESET) { 52 reset = SOCFPGA_RESET(EMAC1); 53 } else if (of_reset_id == EMAC2_RESET) { 54 reset = SOCFPGA_RESET(EMAC2); 55 } else { 56 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); 57 return; 58 } 59 60 clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], 61 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, 62 phymode); 63 64 /* Release the EMAC controller from reset */ 65 socfpga_per_reset(reset, 0); 66 } 67 #endif 68 69 #if defined(CONFIG_SPL_BUILD) 70 /* 71 + * This function initializes security policies to be consistent across 72 + * all logic units in the Arria 10. 73 + * 74 + * The idea is to set all security policies to be normal, nonsecure 75 + * for all units. 76 + */ 77 static void initialize_security_policies(void) 78 { 79 /* Put OCRAM in non-secure */ 80 writel(0x003f0000, &noc_fw_ocram_base->region0); 81 writel(0x1, &noc_fw_ocram_base->enable); 82 } 83 84 int arch_early_init_r(void) 85 { 86 initialize_security_policies(); 87 88 /* Configure the L2 controller to make SDRAM start at 0 */ 89 writel(0x1, &pl310->pl310_addr_filter_start); 90 91 /* assert reset to all except L4WD0 and L4TIMER0 */ 92 socfpga_per_reset_all(); 93 94 /* configuring the clock based on handoff */ 95 /* TODO: Add call to cm_basic_init() */ 96 97 /* Add device descriptor to FPGA device table */ 98 socfpga_fpga_add(); 99 return 0; 100 } 101 #else 102 int arch_early_init_r(void) 103 { 104 return 0; 105 } 106 #endif 107 108 /* 109 * This function looking the 1st encounter UART peripheral, 110 * and then return its offset of the dedicated/shared IO pin 111 * mux. offset value (zero and above). 112 */ 113 static int find_peripheral_uart(const void *blob, 114 int child, const char *node_name) 115 { 116 int len; 117 fdt_addr_t base_addr = 0; 118 fdt_size_t size; 119 const u32 *cell; 120 u32 value, offset = 0; 121 122 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); 123 if (base_addr != FDT_ADDR_T_NONE) { 124 cell = fdt_getprop(blob, child, "pinctrl-single,pins", 125 &len); 126 if (cell != NULL) { 127 for (; len > 0; len -= (2 * sizeof(u32))) { 128 offset = fdt32_to_cpu(*cell++); 129 value = fdt32_to_cpu(*cell++); 130 /* Found UART peripheral. */ 131 if (value == PINMUX_UART) 132 return offset; 133 } 134 } 135 } 136 return -EINVAL; 137 } 138 139 /* 140 * This function looks up the 1st encounter UART peripheral, 141 * and then return its offset of the dedicated/shared IO pin 142 * mux. UART peripheral is found if the offset is not in negative 143 * value. 144 */ 145 static int is_peripheral_uart_true(const void *blob, 146 int node, const char *child_name) 147 { 148 int child, len; 149 const char *node_name; 150 151 child = fdt_first_subnode(blob, node); 152 153 if (child < 0) 154 return -EINVAL; 155 156 node_name = fdt_get_name(blob, child, &len); 157 158 while (node_name) { 159 if (!strcmp(child_name, node_name)) 160 return find_peripheral_uart(blob, child, node_name); 161 162 child = fdt_next_subnode(blob, child); 163 if (child < 0) 164 break; 165 166 node_name = fdt_get_name(blob, child, &len); 167 } 168 169 return -1; 170 } 171 172 /* 173 * This function looking the 1st encounter UART dedicated IO peripheral, 174 * and then return based address of the 1st encounter UART dedicated 175 * IO peripheral. 176 */ 177 unsigned int dedicated_uart_com_port(const void *blob) 178 { 179 int node; 180 181 node = fdtdec_next_compatible(blob, 0, 182 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); 183 if (node < 0) 184 return 0; 185 186 if (is_peripheral_uart_true(blob, node, "dedicated") >= 0) 187 return SOCFPGA_UART1_ADDRESS; 188 189 return 0; 190 } 191 192 /* 193 * This function looking the 1st encounter UART shared IO peripheral, and then 194 * return based address of the 1st encounter UART shared IO peripheral. 195 */ 196 unsigned int shared_uart_com_port(const void *blob) 197 { 198 int node, ret; 199 200 node = fdtdec_next_compatible(blob, 0, 201 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); 202 if (node < 0) 203 return 0; 204 205 ret = is_peripheral_uart_true(blob, node, "shared"); 206 207 if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 || 208 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 || 209 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3) 210 return SOCFPGA_UART0_ADDRESS; 211 else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 || 212 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 || 213 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3) 214 return SOCFPGA_UART1_ADDRESS; 215 216 return 0; 217 } 218 219 /* 220 * This function looking the 1st encounter UART peripheral, and then return 221 * base address of the 1st encounter UART peripheral. 222 */ 223 unsigned int uart_com_port(const void *blob) 224 { 225 unsigned int ret; 226 227 ret = dedicated_uart_com_port(blob); 228 229 if (ret) 230 return ret; 231 232 return shared_uart_com_port(blob); 233 } 234 235 /* 236 * Print CPU information 237 */ 238 #if defined(CONFIG_DISPLAY_CPUINFO) 239 int print_cpuinfo(void) 240 { 241 const u32 bsel = 242 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); 243 244 puts("CPU: Altera SoCFPGA Arria 10\n"); 245 246 printf("BOOT: %s\n", bsel_str[bsel].name); 247 return 0; 248 } 249 #endif 250 251 #ifdef CONFIG_ARCH_MISC_INIT 252 int arch_misc_init(void) 253 { 254 return 0; 255 } 256 #endif 257