xref: /openbmc/u-boot/arch/arm/mach-rockchip/Kconfig (revision dd1033e4)
1if ARCH_ROCKCHIP
2
3config ROCKCHIP_RK3036
4	bool "Support Rockchip RK3036"
5	select CPU_V7A
6	select SUPPORT_SPL
7	select SPL
8	imply USB_FUNCTION_ROCKUSB
9	imply CMD_ROCKUSB
10	help
11	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12	  including NEON and GPU, Mali-400 graphics, several DDR3 options
13	  and video codec support. Peripherals include Gigabit Ethernet,
14	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
16config ROCKCHIP_RK3128
17	bool "Support Rockchip RK3128"
18	select CPU_V7A
19	help
20	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21	  including NEON and GPU, Mali-400 graphics, several DDR3 options
22	  and video codec support. Peripherals include Gigabit Ethernet,
23	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
25config ROCKCHIP_RK3188
26	bool "Support Rockchip RK3188"
27	select CPU_V7A
28	select SPL_BOARD_INIT if SPL
29	select SUPPORT_SPL
30	select SPL
31	select SPL_CLK
32	select SPL_PINCTRL
33	select SPL_REGMAP
34	select SPL_SYSCON
35	select SPL_RAM
36	select SPL_DRIVERS_MISC_SUPPORT
37	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
38	select DEBUG_UART_BOARD_INIT
39	select BOARD_LATE_INIT
40	select ROCKCHIP_BROM_HELPER
41	help
42	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
43	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44	  video interfaces, several memory options and video codec support.
45	  Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
46	  UART, SPI, I2C and PWMs.
47
48config ROCKCHIP_RK322X
49	bool "Support Rockchip RK3228/RK3229"
50	select CPU_V7A
51	select SUPPORT_SPL
52	select SPL
53	select ROCKCHIP_BROM_HELPER
54	select DEBUG_UART_BOARD_INIT
55	help
56	  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
57	  including NEON and GPU, Mali-400 graphics, several DDR3 options
58	  and video codec support. Peripherals include Gigabit Ethernet,
59	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
60
61config ROCKCHIP_RK3288
62	bool "Support Rockchip RK3288"
63	select CPU_V7A
64	select SPL_BOARD_INIT if SPL
65	select SUPPORT_SPL
66	select SPL
67	imply USB_FUNCTION_ROCKUSB
68	imply CMD_ROCKUSB
69	help
70	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
71	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
72	  video interfaces supporting HDMI and eDP, several DDR3 options
73	  and video codec support. Peripherals include Gigabit Ethernet,
74	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
75
76if ROCKCHIP_RK3288
77
78config TPL_LDSCRIPT
79	default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
80
81config TPL_TEXT_BASE
82	default 0xff704000
83
84endif
85
86config ROCKCHIP_RK3328
87	bool "Support Rockchip RK3328"
88	select ARM64
89	help
90	  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
91	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
92	  video interfaces supporting HDMI and eDP, several DDR3 options
93	  and video codec support. Peripherals include Gigabit Ethernet,
94	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
95
96config ROCKCHIP_RK3368
97	bool "Support Rockchip RK3368"
98	select ARM64
99	select SUPPORT_SPL
100	select SUPPORT_TPL
101	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
102	select TPL_NEEDS_SEPARATE_STACK if TPL
103	imply SPL_SEPARATE_BSS
104	imply SPL_SERIAL_SUPPORT
105	imply TPL_SERIAL_SUPPORT
106	select DEBUG_UART_BOARD_INIT
107	help
108	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
109	  into a big and little cluster with 4 cores each) Cortex-A53 including
110	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
111	  (for the little cluster), PowerVR G6110 based graphics, one video
112	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
113	  video codec support.
114
115	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
116	  I2S, UARTs, SPI, I2C and PWMs.
117
118if ROCKCHIP_RK3368
119
120config TPL_LDSCRIPT
121	default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
122
123config TPL_TEXT_BASE
124        default 0xff8c1000
125
126config TPL_MAX_SIZE
127        default 28672
128
129config TPL_STACK
130        default 0xff8cffff
131
132endif
133
134config ROCKCHIP_RK3399
135	bool "Support Rockchip RK3399"
136	select ARM64
137	select SUPPORT_SPL
138	select SPL
139	select SPL_SEPARATE_BSS
140	select SPL_SERIAL_SUPPORT
141	select SPL_DRIVERS_MISC_SUPPORT
142	select DEBUG_UART_BOARD_INIT
143	select BOARD_LATE_INIT
144	select ROCKCHIP_BROM_HELPER
145	help
146	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
147	  and quad-core Cortex-A53.
148	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
149	  video interfaces supporting HDMI and eDP, several DDR3 options
150	  and video codec support. Peripherals include Gigabit Ethernet,
151	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
152
153config ROCKCHIP_RV1108
154	bool "Support Rockchip RV1108"
155	select CPU_V7A
156	help
157	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
158	  and a DSP.
159
160config ROCKCHIP_USB_UART
161	bool "Route uart output to usb pins"
162	help
163	  Rockchip SoCs have the ability to route the signals of the debug
164	  uart through the d+ and d- pins of a specific usb phy to enable
165	  some form of closed-case debugging. With this option supported
166	  SoCs will enable this routing as a debug measure.
167
168config SPL_ROCKCHIP_BACK_TO_BROM
169	bool "SPL returns to bootrom"
170	default y if ROCKCHIP_RK3036
171	select ROCKCHIP_BROM_HELPER
172	depends on SPL
173	help
174	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
175          SPL will return to the boot rom, which will then load the U-Boot
176          binary to keep going on.
177
178config TPL_ROCKCHIP_BACK_TO_BROM
179	bool "TPL returns to bootrom"
180	default y if ROCKCHIP_RK3368
181	select ROCKCHIP_BROM_HELPER
182	depends on TPL
183	help
184	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
185          SPL will return to the boot rom, which will then load the U-Boot
186          binary to keep going on.
187
188config ROCKCHIP_BOOT_MODE_REG
189	hex "Rockchip boot mode flag register address"
190	default 0x200081c8 if ROCKCHIP_RK3036
191	default 0x20004040 if ROCKCHIP_RK3188
192	default 0x110005c8 if ROCKCHIP_RK322X
193	default 0xff730094 if ROCKCHIP_RK3288
194	default 0xff738200 if ROCKCHIP_RK3368
195	default 0xff320300 if ROCKCHIP_RK3399
196	default 0x10300580 if ROCKCHIP_RV1108
197	default 0
198	help
199	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
200	  according to the value from this register.
201
202config ROCKCHIP_SPL_RESERVE_IRAM
203	hex "Size of IRAM reserved in SPL"
204	default 0
205	help
206	  SPL may need reserve memory for firmware loaded by SPL, whose load
207	  address is in IRAM and may overlay with SPL text area if not
208	  reserved.
209
210config ROCKCHIP_BROM_HELPER
211	bool
212
213config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
214        bool "SPL requires early-return (for RK3188-style BROM) to BROM"
215	depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
216	help
217	  Some Rockchip BROM variants (e.g. on the RK3188) load the
218	  first stage in segments and enter multiple times. E.g. on
219	  the RK3188, the first 1KB of the first stage are loaded
220	  first and entered; after returning to the BROM, the
221	  remainder of the first stage is loaded, but the BROM
222	  re-enters at the same address/to the same code as previously.
223
224	  This enables support code in the BOOT0 hook for the SPL stage
225	  to allow multiple entries.
226
227config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
228        bool "TPL requires early-return (for RK3188-style BROM) to BROM"
229	depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
230	help
231	  Some Rockchip BROM variants (e.g. on the RK3188) load the
232	  first stage in segments and enter multiple times. E.g. on
233	  the RK3188, the first 1KB of the first stage are loaded
234	  first and entered; after returning to the BROM, the
235	  remainder of the first stage is loaded, but the BROM
236	  re-enters at the same address/to the same code as previously.
237
238	  This enables support code in the BOOT0 hook for the TPL stage
239	  to allow multiple entries.
240
241config SPL_MMC_SUPPORT
242	default y if !SPL_ROCKCHIP_BACK_TO_BROM
243
244source "arch/arm/mach-rockchip/rk3036/Kconfig"
245source "arch/arm/mach-rockchip/rk3128/Kconfig"
246source "arch/arm/mach-rockchip/rk3188/Kconfig"
247source "arch/arm/mach-rockchip/rk322x/Kconfig"
248source "arch/arm/mach-rockchip/rk3288/Kconfig"
249source "arch/arm/mach-rockchip/rk3328/Kconfig"
250source "arch/arm/mach-rockchip/rk3368/Kconfig"
251source "arch/arm/mach-rockchip/rk3399/Kconfig"
252source "arch/arm/mach-rockchip/rv1108/Kconfig"
253endif
254