xref: /openbmc/u-boot/arch/arm/mach-rockchip/Kconfig (revision b3820ba9)
1if ARCH_ROCKCHIP
2
3config ROCKCHIP_RK3036
4	bool "Support Rockchip RK3036"
5	select CPU_V7A
6	select SUPPORT_SPL
7	select SPL
8	imply USB_FUNCTION_ROCKUSB
9	imply CMD_ROCKUSB
10	help
11	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12	  including NEON and GPU, Mali-400 graphics, several DDR3 options
13	  and video codec support. Peripherals include Gigabit Ethernet,
14	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
16config ROCKCHIP_RK3128
17	bool "Support Rockchip RK3128"
18	select CPU_V7A
19	help
20	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21	  including NEON and GPU, Mali-400 graphics, several DDR3 options
22	  and video codec support. Peripherals include Gigabit Ethernet,
23	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
25config ROCKCHIP_RK3188
26	bool "Support Rockchip RK3188"
27	select CPU_V7A
28	select SPL_BOARD_INIT if SPL
29	select SUPPORT_SPL
30	select SPL
31	select SPL_CLK
32	select SPL_REGMAP
33	select SPL_SYSCON
34	select SPL_RAM
35	select SPL_DRIVERS_MISC_SUPPORT
36	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
37	select DEBUG_UART_BOARD_INIT
38	select BOARD_LATE_INIT
39	select ROCKCHIP_BROM_HELPER
40	help
41	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43	  video interfaces, several memory options and video codec support.
44	  Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45	  UART, SPI, I2C and PWMs.
46
47config ROCKCHIP_RK322X
48	bool "Support Rockchip RK3228/RK3229"
49	select CPU_V7A
50	select SUPPORT_SPL
51	select SPL
52	select ROCKCHIP_BROM_HELPER
53	select DEBUG_UART_BOARD_INIT
54	help
55	  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56	  including NEON and GPU, Mali-400 graphics, several DDR3 options
57	  and video codec support. Peripherals include Gigabit Ethernet,
58	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
59
60config ROCKCHIP_RK3288
61	bool "Support Rockchip RK3288"
62	select CPU_V7A
63	select SPL_BOARD_INIT if SPL
64	select SUPPORT_SPL
65	select SPL
66	imply USB_FUNCTION_ROCKUSB
67	imply CMD_ROCKUSB
68	help
69	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
71	  video interfaces supporting HDMI and eDP, several DDR3 options
72	  and video codec support. Peripherals include Gigabit Ethernet,
73	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
74
75if ROCKCHIP_RK3288
76
77config TPL_TEXT_BASE
78	default 0xff704000
79
80config TPL_MAX_SIZE
81	default 32768
82
83endif
84
85config ROCKCHIP_RK3328
86	bool "Support Rockchip RK3328"
87	select ARM64
88	help
89	  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
90	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
91	  video interfaces supporting HDMI and eDP, several DDR3 options
92	  and video codec support. Peripherals include Gigabit Ethernet,
93	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
94
95config ROCKCHIP_RK3368
96	bool "Support Rockchip RK3368"
97	select ARM64
98	select SUPPORT_SPL
99	select SUPPORT_TPL
100	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
101	select TPL_NEEDS_SEPARATE_STACK if TPL
102	imply SPL_SEPARATE_BSS
103	imply SPL_SERIAL_SUPPORT
104	imply TPL_SERIAL_SUPPORT
105	select DEBUG_UART_BOARD_INIT
106	help
107	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
108	  into a big and little cluster with 4 cores each) Cortex-A53 including
109	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
110	  (for the little cluster), PowerVR G6110 based graphics, one video
111	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
112	  video codec support.
113
114	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
115	  I2S, UARTs, SPI, I2C and PWMs.
116
117if ROCKCHIP_RK3368
118
119config TPL_TEXT_BASE
120        default 0xff8c1000
121
122config TPL_MAX_SIZE
123        default 28672
124
125config TPL_STACK
126        default 0xff8cffff
127
128endif
129
130config ROCKCHIP_RK3399
131	bool "Support Rockchip RK3399"
132	select ARM64
133	select SUPPORT_SPL
134	select SPL
135	select SPL_SEPARATE_BSS
136	select SPL_SERIAL_SUPPORT
137	select SPL_DRIVERS_MISC_SUPPORT
138	select DEBUG_UART_BOARD_INIT
139	select BOARD_LATE_INIT
140	select ROCKCHIP_BROM_HELPER
141	help
142	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
143	  and quad-core Cortex-A53.
144	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
145	  video interfaces supporting HDMI and eDP, several DDR3 options
146	  and video codec support. Peripherals include Gigabit Ethernet,
147	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
148
149config ROCKCHIP_RV1108
150	bool "Support Rockchip RV1108"
151	select CPU_V7A
152	help
153	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
154	  and a DSP.
155
156config ROCKCHIP_USB_UART
157	bool "Route uart output to usb pins"
158	help
159	  Rockchip SoCs have the ability to route the signals of the debug
160	  uart through the d+ and d- pins of a specific usb phy to enable
161	  some form of closed-case debugging. With this option supported
162	  SoCs will enable this routing as a debug measure.
163
164config SPL_ROCKCHIP_BACK_TO_BROM
165	bool "SPL returns to bootrom"
166	default y if ROCKCHIP_RK3036
167	select ROCKCHIP_BROM_HELPER
168	depends on SPL
169	help
170	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
171          SPL will return to the boot rom, which will then load the U-Boot
172          binary to keep going on.
173
174config TPL_ROCKCHIP_BACK_TO_BROM
175	bool "TPL returns to bootrom"
176	default y if ROCKCHIP_RK3368
177	select ROCKCHIP_BROM_HELPER
178	depends on TPL
179	help
180	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
181          SPL will return to the boot rom, which will then load the U-Boot
182          binary to keep going on.
183
184config ROCKCHIP_BOOT_MODE_REG
185	hex "Rockchip boot mode flag register address"
186	default 0x200081c8 if ROCKCHIP_RK3036
187	default 0x20004040 if ROCKCHIP_RK3188
188	default 0x110005c8 if ROCKCHIP_RK322X
189	default 0xff730094 if ROCKCHIP_RK3288
190	default 0xff738200 if ROCKCHIP_RK3368
191	default 0xff320300 if ROCKCHIP_RK3399
192	default 0x10300580 if ROCKCHIP_RV1108
193	default 0
194	help
195	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
196	  according to the value from this register.
197
198config ROCKCHIP_SPL_RESERVE_IRAM
199	hex "Size of IRAM reserved in SPL"
200	default 0
201	help
202	  SPL may need reserve memory for firmware loaded by SPL, whose load
203	  address is in IRAM and may overlay with SPL text area if not
204	  reserved.
205
206config ROCKCHIP_BROM_HELPER
207	bool
208
209config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
210        bool "SPL requires early-return (for RK3188-style BROM) to BROM"
211	depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
212	help
213	  Some Rockchip BROM variants (e.g. on the RK3188) load the
214	  first stage in segments and enter multiple times. E.g. on
215	  the RK3188, the first 1KB of the first stage are loaded
216	  first and entered; after returning to the BROM, the
217	  remainder of the first stage is loaded, but the BROM
218	  re-enters at the same address/to the same code as previously.
219
220	  This enables support code in the BOOT0 hook for the SPL stage
221	  to allow multiple entries.
222
223config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
224        bool "TPL requires early-return (for RK3188-style BROM) to BROM"
225	depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
226	help
227	  Some Rockchip BROM variants (e.g. on the RK3188) load the
228	  first stage in segments and enter multiple times. E.g. on
229	  the RK3188, the first 1KB of the first stage are loaded
230	  first and entered; after returning to the BROM, the
231	  remainder of the first stage is loaded, but the BROM
232	  re-enters at the same address/to the same code as previously.
233
234	  This enables support code in the BOOT0 hook for the TPL stage
235	  to allow multiple entries.
236
237config SPL_MMC_SUPPORT
238	default y if !SPL_ROCKCHIP_BACK_TO_BROM
239
240source "arch/arm/mach-rockchip/rk3036/Kconfig"
241source "arch/arm/mach-rockchip/rk3128/Kconfig"
242source "arch/arm/mach-rockchip/rk3188/Kconfig"
243source "arch/arm/mach-rockchip/rk322x/Kconfig"
244source "arch/arm/mach-rockchip/rk3288/Kconfig"
245source "arch/arm/mach-rockchip/rk3328/Kconfig"
246source "arch/arm/mach-rockchip/rk3368/Kconfig"
247source "arch/arm/mach-rockchip/rk3399/Kconfig"
248source "arch/arm/mach-rockchip/rv1108/Kconfig"
249endif
250