xref: /openbmc/u-boot/arch/arm/mach-rockchip/Kconfig (revision 5b5ca4c0)
1if ARCH_ROCKCHIP
2
3config ROCKCHIP_RK3036
4	bool "Support Rockchip RK3036"
5	select CPU_V7A
6	select SUPPORT_SPL
7	select SPL
8	imply USB_FUNCTION_ROCKUSB
9	imply CMD_ROCKUSB
10	help
11	  The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12	  including NEON and GPU, Mali-400 graphics, several DDR3 options
13	  and video codec support. Peripherals include Gigabit Ethernet,
14	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
16config ROCKCHIP_RK3128
17	bool "Support Rockchip RK3128"
18	select CPU_V7A
19	help
20	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21	  including NEON and GPU, Mali-400 graphics, several DDR3 options
22	  and video codec support. Peripherals include Gigabit Ethernet,
23	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
25config ROCKCHIP_RK3188
26	bool "Support Rockchip RK3188"
27	select CPU_V7A
28	select SPL_BOARD_INIT if SPL
29	select SUPPORT_SPL
30	select SPL
31	select SPL_CLK
32	select SPL_PINCTRL
33	select SPL_REGMAP
34	select SPL_SYSCON
35	select SPL_RAM
36	select SPL_DRIVERS_MISC_SUPPORT
37	select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
38	select BOARD_LATE_INIT
39	select ROCKCHIP_BROM_HELPER
40	help
41	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43	  video interfaces, several memory options and video codec support.
44	  Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45	  UART, SPI, I2C and PWMs.
46
47config ROCKCHIP_RK322X
48	bool "Support Rockchip RK3228/RK3229"
49	select CPU_V7A
50	select SUPPORT_SPL
51	select SPL
52	select ROCKCHIP_BROM_HELPER
53	select DEBUG_UART_BOARD_INIT
54	help
55	  The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56	  including NEON and GPU, Mali-400 graphics, several DDR3 options
57	  and video codec support. Peripherals include Gigabit Ethernet,
58	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
59
60config ROCKCHIP_RK3288
61	bool "Support Rockchip RK3288"
62	select CPU_V7A
63	select SPL_BOARD_INIT if SPL
64	select SUPPORT_SPL
65	select SPL
66	imply USB_FUNCTION_ROCKUSB
67	imply CMD_ROCKUSB
68	help
69	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
71	  video interfaces supporting HDMI and eDP, several DDR3 options
72	  and video codec support. Peripherals include Gigabit Ethernet,
73	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
74
75if ROCKCHIP_RK3288
76
77config TPL_LDSCRIPT
78	default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
79
80config TPL_TEXT_BASE
81	default 0xff704000
82
83endif
84
85config ROCKCHIP_RK3328
86	bool "Support Rockchip RK3328"
87	select ARM64
88	help
89	  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
90	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
91	  video interfaces supporting HDMI and eDP, several DDR3 options
92	  and video codec support. Peripherals include Gigabit Ethernet,
93	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
94
95config ROCKCHIP_RK3368
96	bool "Support Rockchip RK3368"
97	select ARM64
98	select SUPPORT_SPL
99	select SUPPORT_TPL
100	select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
101	select TPL_NEEDS_SEPARATE_STACK if TPL
102	imply SPL_SEPARATE_BSS
103	imply SPL_SERIAL_SUPPORT
104	imply TPL_SERIAL_SUPPORT
105	select DEBUG_UART_BOARD_INIT
106	help
107	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
108	  into a big and little cluster with 4 cores each) Cortex-A53 including
109	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
110	  (for the little cluster), PowerVR G6110 based graphics, one video
111	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
112	  video codec support.
113
114	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
115	  I2S, UARTs, SPI, I2C and PWMs.
116
117if ROCKCHIP_RK3368
118
119config TPL_LDSCRIPT
120	default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
121
122config TPL_TEXT_BASE
123        default 0xff8c1000
124
125config TPL_MAX_SIZE
126        default 28672
127
128config TPL_STACK
129        default 0xff8cffff
130
131endif
132
133config ROCKCHIP_RK3399
134	bool "Support Rockchip RK3399"
135	select ARM64
136	select SUPPORT_SPL
137	select SPL
138	select SPL_SEPARATE_BSS
139	select SPL_SERIAL_SUPPORT
140	select SPL_DRIVERS_MISC_SUPPORT
141	select DEBUG_UART_BOARD_INIT
142	select BOARD_LATE_INIT
143	select ROCKCHIP_BROM_HELPER
144	help
145	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
146	  and quad-core Cortex-A53.
147	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
148	  video interfaces supporting HDMI and eDP, several DDR3 options
149	  and video codec support. Peripherals include Gigabit Ethernet,
150	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
151
152config ROCKCHIP_RV1108
153	bool "Support Rockchip RV1108"
154	select CPU_V7A
155	help
156	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
157	  and a DSP.
158
159config ROCKCHIP_USB_UART
160	bool "Route uart output to usb pins"
161	help
162	  Rockchip SoCs have the ability to route the signals of the debug
163	  uart through the d+ and d- pins of a specific usb phy to enable
164	  some form of closed-case debugging. With this option supported
165	  SoCs will enable this routing as a debug measure.
166
167config SPL_ROCKCHIP_BACK_TO_BROM
168	bool "SPL returns to bootrom"
169	default y if ROCKCHIP_RK3036
170	select ROCKCHIP_BROM_HELPER
171	depends on SPL
172	help
173	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
174          SPL will return to the boot rom, which will then load the U-Boot
175          binary to keep going on.
176
177config TPL_ROCKCHIP_BACK_TO_BROM
178	bool "TPL returns to bootrom"
179	default y if ROCKCHIP_RK3368
180	select ROCKCHIP_BROM_HELPER
181	depends on TPL
182	help
183	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
184          SPL will return to the boot rom, which will then load the U-Boot
185          binary to keep going on.
186
187config ROCKCHIP_BOOT_MODE_REG
188	hex "Rockchip boot mode flag register address"
189	default 0x200081c8 if ROCKCHIP_RK3036
190	default 0x20004040 if ROCKCHIP_RK3188
191	default 0x110005c8 if ROCKCHIP_RK322X
192	default 0xff730094 if ROCKCHIP_RK3288
193	default 0xff738200 if ROCKCHIP_RK3368
194	default 0xff320300 if ROCKCHIP_RK3399
195	default 0x10300580 if ROCKCHIP_RV1108
196	default 0
197	help
198	  The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
199	  according to the value from this register.
200
201config ROCKCHIP_SPL_RESERVE_IRAM
202	hex "Size of IRAM reserved in SPL"
203	default 0
204	help
205	  SPL may need reserve memory for firmware loaded by SPL, whose load
206	  address is in IRAM and may overlay with SPL text area if not
207	  reserved.
208
209config ROCKCHIP_BROM_HELPER
210	bool
211
212config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
213        bool "SPL requires early-return (for RK3188-style BROM) to BROM"
214	depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
215	help
216	  Some Rockchip BROM variants (e.g. on the RK3188) load the
217	  first stage in segments and enter multiple times. E.g. on
218	  the RK3188, the first 1KB of the first stage are loaded
219	  first and entered; after returning to the BROM, the
220	  remainder of the first stage is loaded, but the BROM
221	  re-enters at the same address/to the same code as previously.
222
223	  This enables support code in the BOOT0 hook for the SPL stage
224	  to allow multiple entries.
225
226config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
227        bool "TPL requires early-return (for RK3188-style BROM) to BROM"
228	depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
229	help
230	  Some Rockchip BROM variants (e.g. on the RK3188) load the
231	  first stage in segments and enter multiple times. E.g. on
232	  the RK3188, the first 1KB of the first stage are loaded
233	  first and entered; after returning to the BROM, the
234	  remainder of the first stage is loaded, but the BROM
235	  re-enters at the same address/to the same code as previously.
236
237	  This enables support code in the BOOT0 hook for the TPL stage
238	  to allow multiple entries.
239
240config SPL_MMC_SUPPORT
241	default y if !SPL_ROCKCHIP_BACK_TO_BROM
242
243source "arch/arm/mach-rockchip/rk3036/Kconfig"
244source "arch/arm/mach-rockchip/rk3128/Kconfig"
245source "arch/arm/mach-rockchip/rk3188/Kconfig"
246source "arch/arm/mach-rockchip/rk322x/Kconfig"
247source "arch/arm/mach-rockchip/rk3288/Kconfig"
248source "arch/arm/mach-rockchip/rk3328/Kconfig"
249source "arch/arm/mach-rockchip/rk3368/Kconfig"
250source "arch/arm/mach-rockchip/rk3399/Kconfig"
251source "arch/arm/mach-rockchip/rv1108/Kconfig"
252endif
253