1 /* 2 * Copyright (C) 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/atmel_mpddrc.h> 11 12 static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr, 13 int mode, 14 u32 ram_address) 15 { 16 writel(mode, &mpddr->mr); 17 writel(0, ram_address); 18 } 19 20 static int ddr2_decodtype_is_seq(u32 cr) 21 { 22 #if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ 23 defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) 24 if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) 25 return 0; 26 #endif 27 return 1; 28 } 29 30 31 int ddr2_init(const unsigned int base, 32 const unsigned int ram_address, 33 const struct atmel_mpddr *mpddr_value) 34 { 35 const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base; 36 37 u32 ba_off, cr; 38 39 /* Compute bank offset according to NC in configuration register */ 40 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; 41 if (ddr2_decodtype_is_seq(mpddr_value->cr)) 42 ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; 43 44 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; 45 46 /* Program the memory device type into the memory device register */ 47 writel(mpddr_value->md, &mpddr->md); 48 49 /* Program the configuration register */ 50 writel(mpddr_value->cr, &mpddr->cr); 51 52 /* Program the timing register */ 53 writel(mpddr_value->tpr0, &mpddr->tpr0); 54 writel(mpddr_value->tpr1, &mpddr->tpr1); 55 writel(mpddr_value->tpr2, &mpddr->tpr2); 56 57 /* Issue a NOP command */ 58 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); 59 60 /* A 200 us is provided to precede any signal toggle */ 61 udelay(200); 62 63 /* Issue a NOP command */ 64 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); 65 66 /* Issue an all banks precharge command */ 67 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); 68 69 /* Issue an extended mode register set(EMRS2) to choose operation */ 70 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 71 ram_address + (0x2 << ba_off)); 72 73 /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ 74 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 75 ram_address + (0x3 << ba_off)); 76 77 /* 78 * Issue an extended mode register set(EMRS1) to enable DLL and 79 * program D.I.C (output driver impedance control) 80 */ 81 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 82 ram_address + (0x1 << ba_off)); 83 84 /* Enable DLL reset */ 85 cr = readl(&mpddr->cr); 86 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); 87 88 /* A mode register set(MRS) cycle is issued to reset DLL */ 89 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); 90 91 /* Issue an all banks precharge command */ 92 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); 93 94 /* Two auto-refresh (CBR) cycles are provided */ 95 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); 96 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); 97 98 /* Disable DLL reset */ 99 cr = readl(&mpddr->cr); 100 writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); 101 102 /* A mode register set (MRS) cycle is issued to disable DLL reset */ 103 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); 104 105 /* Set OCD calibration in default state */ 106 cr = readl(&mpddr->cr); 107 writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); 108 109 /* 110 * An extended mode register set (EMRS1) cycle is issued 111 * to OCD default value 112 */ 113 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 114 ram_address + (0x1 << ba_off)); 115 116 /* OCD calibration mode exit */ 117 cr = readl(&mpddr->cr); 118 writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); 119 120 /* 121 * An extended mode register set (EMRS1) cycle is issued 122 * to enable OCD exit 123 */ 124 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, 125 ram_address + (0x1 << ba_off)); 126 127 /* A nornal mode command is provided */ 128 atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); 129 130 /* Perform a write access to any DDR2-SDRAM address */ 131 writel(0, ram_address); 132 133 /* Write the refresh rate */ 134 writel(mpddr_value->rtr, &mpddr->rtr); 135 136 return 0; 137 } 138