1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  * Ryan Chen <ryan_chen@aspeedtech.com>
5  */
6 
7 #include <common.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <asm/arch/aspeed_scu_info.h>
11 
12 /* SoC mapping Table */
13 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, }
14 
15 struct soc_id {
16 	const char *name;
17 	u64 rev_id;
18 };
19 
20 static struct soc_id soc_map_table[] = {
21 	SOC_ID("AST2600-A0", 0x0500030305000303),
22 	SOC_ID("AST2600-A1", 0x0501030305010303),
23 	SOC_ID("AST2620-A1", 0x0501020305010203),
24 	SOC_ID("AST2600-A2", 0x0502030305010303),
25 	SOC_ID("AST2620-A2", 0x0502020305010203),
26 	SOC_ID("AST2605-A2", 0x0502010305010103),
27 	SOC_ID("AST2600-A3", 0x0503030305030303),
28 	SOC_ID("AST2620-A3", 0x0503020305030203),
29 	SOC_ID("AST2605-A3", 0x0503010305030103),
30 };
31 
32 void aspeed_print_soc_id(void)
33 {
34 	int i;
35 	u64 rev_id;
36 
37 	rev_id = readl(ASPEED_REVISION_ID0);
38 	rev_id = ((u64)readl(ASPEED_REVISION_ID1) << 32) | rev_id;
39 
40 	for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) {
41 		if (rev_id == soc_map_table[i].rev_id)
42 			break;
43 	}
44 	if (i == ARRAY_SIZE(soc_map_table))
45 		printf("UnKnow-SOC: %llx\n", rev_id);
46 	else
47 		printf("SOC: %4s \n",soc_map_table[i].name);
48 }
49 
50 int aspeed_get_mac_phy_interface(u8 num)
51 {
52 	u32 strap1 = readl(ASPEED_HW_STRAP1);
53 #ifdef ASPEED_HW_STRAP2
54 	u32 strap2 = readl(ASPEED_HW_STRAP2);
55 #endif
56 	switch(num) {
57 		case 0:
58 			if(strap1 & BIT(6)) {
59 				return 1;
60 			} else {
61 				return 0;
62 			}
63 			break;
64 		case 1:
65 			if(strap1 & BIT(7)) {
66 				return 1;
67 			} else {
68 				return 0;
69 			}
70 			break;
71 #ifdef ASPEED_HW_STRAP2
72 		case 2:
73 			if(strap2 & BIT(0)) {
74 				return 1;
75 			} else {
76 				return 0;
77 			}
78 			break;
79 		case 3:
80 			if(strap2 & BIT(1)) {
81 				return 1;
82 			} else {
83 				return 0;
84 			}
85 			break;
86 #endif
87 	}
88 	return -1;
89 }
90 
91 void aspeed_print_security_info(void)
92 {
93 	u32 qsr = readl(ASPEED_OTP_QSR);
94 	u32 sb_sts = readl(ASPEED_SB_STS);
95 	u32 hash;
96 	u32 rsa;
97 	char alg[20];
98 
99 	if (!(sb_sts & BIT(6)))
100 		return;
101 	printf("Secure Boot: ");
102 	if (qsr & BIT(7)) {
103 		hash = (qsr >> 10) & 3;
104 		rsa = (qsr >> 12) & 3;
105 
106 		if (qsr & BIT(27)) {
107 			sprintf(alg + strlen(alg), "AES_");
108 		}
109 		switch (rsa) {
110 		case 0:
111 			sprintf(alg + strlen(alg), "RSA1024_");
112 			break;
113 		case 1:
114 			sprintf(alg + strlen(alg), "RSA2048_");
115 			break;
116 		case 2:
117 			sprintf(alg + strlen(alg), "RSA3072_");
118 			break;
119 		default:
120 			sprintf(alg + strlen(alg), "RSA4096_");
121 			break;
122 		}
123 		switch (hash) {
124 		case 0:
125 			sprintf(alg + strlen(alg), "SHA224");
126 			break;
127 		case 1:
128 			sprintf(alg + strlen(alg), "SHA256");
129 			break;
130 		case 2:
131 			sprintf(alg + strlen(alg), "SHA384");
132 			break;
133 		default:
134 			sprintf(alg + strlen(alg), "SHA512");
135 			break;
136 		}
137 		printf("Mode_2, %s\n", alg);
138 	} else {
139 		printf("Mode_GCM\n");
140 		return;
141 	}
142 }
143 
144 /*	ASPEED_SYS_RESET_CTRL	: System reset contrl/status register*/
145 #define SYS_WDT8_SW_RESET	BIT(15)
146 #define SYS_WDT8_ARM_RESET	BIT(14)
147 #define SYS_WDT8_FULL_RESET	BIT(13)
148 #define SYS_WDT8_SOC_RESET	BIT(12)
149 #define SYS_WDT7_SW_RESET	BIT(11)
150 #define SYS_WDT7_ARM_RESET	BIT(10)
151 #define SYS_WDT7_FULL_RESET	BIT(9)
152 #define SYS_WDT7_SOC_RESET	BIT(8)
153 #define SYS_WDT6_SW_RESET	BIT(7)
154 #define SYS_WDT6_ARM_RESET	BIT(6)
155 #define SYS_WDT6_FULL_RESET	BIT(5)
156 #define SYS_WDT6_SOC_RESET	BIT(4)
157 #define SYS_WDT5_SW_RESET	BIT(3)
158 #define SYS_WDT5_ARM_RESET	BIT(2)
159 #define SYS_WDT5_FULL_RESET	BIT(1)
160 #define SYS_WDT5_SOC_RESET	BIT(0)
161 
162 #define SYS_WDT4_SW_RESET	BIT(31)
163 #define SYS_WDT4_ARM_RESET	BIT(30)
164 #define SYS_WDT4_FULL_RESET	BIT(29)
165 #define SYS_WDT4_SOC_RESET	BIT(28)
166 #define SYS_WDT3_SW_RESET	BIT(27)
167 #define SYS_WDT3_ARM_RESET	BIT(26)
168 #define SYS_WDT3_FULL_RESET	BIT(25)
169 #define SYS_WDT3_SOC_RESET	BIT(24)
170 #define SYS_WDT2_SW_RESET	BIT(23)
171 #define SYS_WDT2_ARM_RESET	BIT(22)
172 #define SYS_WDT2_FULL_RESET	BIT(21)
173 #define SYS_WDT2_SOC_RESET	BIT(20)
174 #define SYS_WDT1_SW_RESET	BIT(19)
175 #define SYS_WDT1_ARM_RESET	BIT(18)
176 #define SYS_WDT1_FULL_RESET	BIT(17)
177 #define SYS_WDT1_SOC_RESET	BIT(16)
178 
179 #define SYS_CM3_EXT_RESET	BIT(6)
180 #define SYS_PCI2_RESET		BIT(5)
181 #define SYS_PCI1_RESET		BIT(4)
182 #define SYS_DRAM_ECC_RESET	BIT(3)
183 #define SYS_FLASH_ABR_RESET	BIT(2)
184 #define SYS_EXT_RESET		BIT(1)
185 #define SYS_PWR_RESET_FLAG	BIT(0)
186 
187 #define BIT_WDT_SOC(x)	SYS_WDT ## x ## _SOC_RESET
188 #define BIT_WDT_FULL(x)	SYS_WDT ## x ## _FULL_RESET
189 #define BIT_WDT_ARM(x)	SYS_WDT ## x ## _ARM_RESET
190 #define BIT_WDT_SW(x)	SYS_WDT ## x ## _SW_RESET
191 
192 #define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \
193 	if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \
194 		printf("RST: WDT%d ", x); \
195 		if (event_log & BIT_WDT_SOC(x)) { \
196 			printf("SOC "); \
197 			writel(BIT_WDT_SOC(x), event_log_reg); \
198 		} \
199 		if (event_log & BIT_WDT_FULL(x)) { \
200 			printf("FULL "); \
201 			writel(BIT_WDT_FULL(x), event_log_reg); \
202 		} \
203 		if (event_log & BIT_WDT_ARM(x)) { \
204 			printf("ARM "); \
205 			writel(BIT_WDT_ARM(x), event_log_reg); \
206 		} \
207 		if (event_log & BIT_WDT_SW(x)) { \
208 			printf("SW "); \
209 			writel(BIT_WDT_SW(x), event_log_reg); \
210 		} \
211 		printf("\n"); \
212 	} \
213 	(void)(x)
214 
215 void aspeed_print_sysrst_info(void)
216 {
217 	u32 rest = readl(ASPEED_SYS_RESET_CTRL);
218 	u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3);
219 
220 	if (rest & SYS_PWR_RESET_FLAG) {
221 		printf("RST: Power On \n");
222 		writel(rest, ASPEED_SYS_RESET_CTRL);
223 	} else {
224 		HANDLE_WDTx_RESET(8, rest3, ASPEED_SYS_RESET_CTRL3);
225 		HANDLE_WDTx_RESET(7, rest3, ASPEED_SYS_RESET_CTRL3);
226 		HANDLE_WDTx_RESET(6, rest3, ASPEED_SYS_RESET_CTRL3);
227 		HANDLE_WDTx_RESET(5, rest3, ASPEED_SYS_RESET_CTRL3);
228 		HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL);
229 		HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL);
230 		HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL);
231 		HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL);
232 
233 		if (rest & SYS_CM3_EXT_RESET) {
234 			printf("RST: SYS_CM3_EXT_RESET \n");
235 			writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL);
236 		}
237 
238 		if (rest & (SYS_PCI1_RESET | SYS_PCI2_RESET)) {
239 			printf("PCI RST: ");
240 			if (rest & SYS_PCI1_RESET) {
241 				printf("#1 ");
242 				writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL);
243 			}
244 
245 			if (rest & SYS_PCI2_RESET) {
246 				printf("#2 ");
247 				writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL);
248 			}
249 			printf("\n");
250 		}
251 
252 		if (rest & SYS_DRAM_ECC_RESET) {
253 			printf("RST: DRAM_ECC_RESET \n");
254 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
255 		}
256 
257 		if (rest & SYS_FLASH_ABR_RESET) {
258 			printf("RST: SYS_FLASH_ABR_RESET \n");
259 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
260 		}
261 		if (rest & SYS_EXT_RESET) {
262 			printf("RST: External \n");
263 			writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL);
264 		}
265 	}
266 }
267 
268 #define SOC_FW_INIT_DRAM		BIT(7)
269 
270 void aspeed_print_dram_initializer(void)
271 {
272 	if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM)
273 		printf("[init by SOC]\n");
274 	else
275 		printf("[init by VBIOS]\n");
276 }
277 
278 void aspeed_print_2nd_wdt_mode(void)
279 {
280 	/* ABR enable */
281 	if (readl(ASPEED_HW_STRAP2) & BIT(11)) {
282 		/* boot from eMMC */
283 		if (readl(ASPEED_HW_STRAP1) & BIT(2)) {
284 			printf("eMMC 2nd Boot (ABR): Enable");
285 			printf(", boot partition: %s", \
286 				readl(ASPEED_EMMC_WDT_CTRL) & BIT(4) ? "2" : "1");
287 			printf("\n");
288 		} else { /* boot from SPI */
289 			printf("FMC 2nd Boot (ABR): Enable");
290 			if (readl(ASPEED_HW_STRAP2) & BIT(12))
291 				printf(", Single flash");
292 			else
293 				printf(", Dual flashes");
294 
295 			printf(", Source: %s", \
296 					readl(ASPEED_FMC_WDT2) & BIT(4) ? "Alternate" : "Primary");
297 
298 			if (readl(ASPEED_HW_STRAP2) & GENMASK(15, 13))
299 				printf(", bspi_size: %ld MB", \
300 					BIT((readl(ASPEED_HW_STRAP2) >> 13) & 0x7));
301 
302 			printf("\n");
303 		}
304 	}
305 }
306 
307 void aspeed_print_fmc_aux_ctrl(void)
308 {
309 
310 	if (readl(ASPEED_HW_STRAP2) & BIT(22)) {
311 		printf("FMC aux control: Enable");
312 		/* gpioY6 : BSPI_ABR */
313 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(6))
314 			printf(", Force Alt boot");
315 
316 		/* gpioY7 : BSPI_WP_N */
317 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)))
318 			printf(", BSPI_WP: Enable");
319 
320 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)) && \
321 			(readl(ASPEED_HW_STRAP2) & GENMASK(24, 23)) != 0) {
322 			printf(", FMC HW CRTM: Enable, size: %ld KB", \
323 					BIT((readl(ASPEED_HW_STRAP2) >> 23) & 0x3) * 128);
324 		}
325 
326 		printf("\n");
327 	}
328 }
329 
330 void aspeed_print_spi1_abr_mode(void)
331 {
332 	if (readl(ASPEED_HW_STRAP2) & BIT(16)) {
333 		printf("SPI1 ABR: Enable");
334 		if(readl(ASPEED_SPI1_BOOT_CTRL) & BIT(6))
335 			printf(", Single flash");
336 		else
337 			printf(", Dual flashes");
338 
339 		printf(", Source : %s", \
340 				readl(ASPEED_SPI1_BOOT_CTRL) & BIT(4) ? "Alternate" : "Primary");
341 
342 		if (readl(ASPEED_SPI1_BOOT_CTRL) & GENMASK(3, 1))
343 			printf(", hspi_size : %ld MB", \
344 				BIT((readl(ASPEED_SPI1_BOOT_CTRL) >> 1) & 0x7));
345 
346 		printf("\n");
347 	}
348 
349 	if (readl(ASPEED_HW_STRAP2) & BIT(17)) {
350 		printf("SPI1 select pin: Enable");
351 		/* gpioZ1 : HSPI_ABR */
352 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9))
353 			printf(", Force Alt boot");
354 
355 		printf("\n");
356 	}
357 }
358 
359 void aspeed_print_spi1_aux_ctrl(void)
360 {
361 	if (readl(ASPEED_HW_STRAP2) & BIT(27)) {
362 		printf("SPI1 aux control: Enable");
363 		/* gpioZ1 : HSPI_ABR */
364 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9))
365 			printf(", Force Alt boot");
366 
367 		/* gpioZ2: BSPI_WP_N */
368 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)))
369 			printf(", HPI_WP: Enable");
370 
371 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)) && \
372 			(readl(ASPEED_HW_STRAP2) & GENMASK(26, 25)) != 0) {
373 			printf(", SPI1 HW CRTM: Enable, size: %ld KB", \
374 					BIT((readl(ASPEED_HW_STRAP2) >> 25) & 0x3) * 128);
375 		}
376 
377 		printf("\n");
378 	}
379 }
380 
381 void aspeed_print_spi_strap_mode(void)
382 {
383 	if(readl(ASPEED_HW_STRAP2) & BIT(10))
384 		printf("SPI: 3/4 byte mode auto detection \n");
385 }
386 
387 void aspeed_print_espi_mode(void)
388 {
389 	int espi_mode = 0;
390 	int sio_disable = 0;
391 	u32 sio_addr = 0x2e;
392 
393 	if (readl(ASPEED_HW_STRAP2) & BIT(6))
394 		espi_mode = 0;
395 	else
396 		espi_mode = 1;
397 
398 	if (readl(ASPEED_HW_STRAP2) & BIT(2))
399 		sio_addr = 0x4e;
400 
401 	if (readl(ASPEED_HW_STRAP2) & BIT(3))
402 		sio_disable = 1;
403 
404 	if (espi_mode)
405 		printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
406 	else
407 		printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
408 
409 	if (!sio_disable)
410 		printf(": SuperIO-%02x\n", sio_addr);
411 	else
412 		printf("\n");
413 }
414 
415 void aspeed_print_mac_info(void)
416 {
417 	int i;
418 	printf("Eth: ");
419 	for (i = 0; i < ASPEED_MAC_COUNT; i++) {
420 		printf("MAC%d: %s", i,
421 				aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI");
422 		if (i != (ASPEED_MAC_COUNT -1))
423 			printf(", ");
424 	}
425 	printf("\n");
426 }
427