1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  * Ryan Chen <ryan_chen@aspeedtech.com>
5  */
6 
7 #include <common.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <asm/arch/aspeed_scu_info.h>
11 
12 /* SoC mapping Table */
13 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, }
14 
15 struct soc_id {
16 	const char *name;
17 	u32	   rev_id;
18 };
19 
20 static struct soc_id soc_map_table[] = {
21 	SOC_ID("AST1100/AST2050-A0", 0x00000200),
22 	SOC_ID("AST1100/AST2050-A1", 0x00000201),
23 	SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202),
24 	SOC_ID("AST1510/AST2100-A0", 0x00000300),
25 	SOC_ID("AST1510/AST2100-A1", 0x00000301),
26 	SOC_ID("AST1510/AST2100-A2,3", 0x00000302),
27 	SOC_ID("AST2200-A0,1", 0x00000102),
28 	SOC_ID("AST2300-A0", 0x01000003),
29 	SOC_ID("AST2300-A1", 0x01010303),
30 	SOC_ID("AST1300-A1", 0x01010003),
31 	SOC_ID("AST1050-A1", 0x01010203),
32 	SOC_ID("AST2400-A0", 0x02000303),
33 	SOC_ID("AST2400-A1", 0x02010303),
34 	SOC_ID("AST1010-A0", 0x03000003),
35 	SOC_ID("AST1010-A1", 0x03010003),
36 	SOC_ID("AST3200-A0", 0x04002003),
37 	SOC_ID("AST3200-A1", 0x04012003),
38 	SOC_ID("AST3200-A2", 0x04032003),
39 	SOC_ID("AST1520-A0", 0x03000203),
40 	SOC_ID("AST1520-A1", 0x03010203),
41 	SOC_ID("AST2510-A0", 0x04000103),
42 	SOC_ID("AST2510-A1", 0x04010103),
43 	SOC_ID("AST2510-A2", 0x04030103),
44 	SOC_ID("AST2520-A0", 0x04000203),
45 	SOC_ID("AST2520-A1", 0x04010203),
46 	SOC_ID("AST2520-A2", 0x04030203),
47 	SOC_ID("AST2500-A0", 0x04000303),
48 	SOC_ID("AST2500-A1", 0x04010303),
49 	SOC_ID("AST2500-A2", 0x04030303),
50 	SOC_ID("AST2530-A0", 0x04000403),
51 	SOC_ID("AST2530-A1", 0x04010403),
52 	SOC_ID("AST2530-A2", 0x04030403),
53 	SOC_ID("AST2600-A0", 0x05000303),
54 };
55 
56 void aspeed_print_soc_id(void)
57 {
58 	int i;
59 	u32 rev_id = readl(ASPEED_REVISION_ID);
60 	for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) {
61 		if (rev_id == soc_map_table[i].rev_id)
62 			break;
63 	}
64 	if (i == ARRAY_SIZE(soc_map_table))
65 		printf("UnKnow-SOC: %x \n",rev_id);
66 	else
67 		printf("SOC: %4s \n",soc_map_table[i].name);
68 }
69 
70 int aspeed_get_mac_phy_interface(u8 num)
71 {
72 	u32 strap1 = readl(ASPEED_HW_STRAP1);
73 #ifdef ASPEED_HW_STRAP2
74 	u32 strap2 = readl(ASPEED_HW_STRAP2);
75 #endif
76 	switch(num) {
77 		case 0:
78 			if(strap1 & BIT(6)) {
79 				return 1;
80 			} else {
81 				return 0;
82 			}
83 			break;
84 		case 1:
85 			if(strap1 & BIT(7)) {
86 				return 1;
87 			} else {
88 				return 0;
89 			}
90 			break;
91 #ifdef ASPEED_HW_STRAP2
92 		case 2:
93 			if(strap2 & BIT(0)) {
94 				return 1;
95 			} else {
96 				return 0;
97 			}
98 			break;
99 		case 3:
100 			if(strap2 & BIT(1)) {
101 				return 1;
102 			} else {
103 				return 0;
104 			}
105 			break;
106 #endif
107 	}
108 	return -1;
109 }
110 
111 void aspeed_print_security_info(void)
112 {
113 	if(readl(ASPEED_HW_STRAP1) & BIT(1))
114 		printf("Security Boot \n");
115 }
116 
117 /*	ASPEED_SYS_RESET_CTRL	: System reset contrl/status register*/
118 #define SYS_WDT8_SW_RESET	BIT(15)
119 #define SYS_WDT8_ARM_RESET	BIT(14)
120 #define SYS_WDT8_FULL_RESET	BIT(13)
121 #define SYS_WDT8_SOC_RESET	BIT(12)
122 #define SYS_WDT7_SW_RESET	BIT(11)
123 #define SYS_WDT7_ARM_RESET	BIT(10)
124 #define SYS_WDT7_FULL_RESET	BIT(9)
125 #define SYS_WDT7_SOC_RESET	BIT(8)
126 #define SYS_WDT6_SW_RESET	BIT(7)
127 #define SYS_WDT6_ARM_RESET	BIT(6)
128 #define SYS_WDT6_FULL_RESET	BIT(5)
129 #define SYS_WDT6_SOC_RESET	BIT(4)
130 #define SYS_WDT5_SW_RESET	BIT(3)
131 #define SYS_WDT5_ARM_RESET	BIT(2)
132 #define SYS_WDT5_FULL_RESET	BIT(1)
133 #define SYS_WDT5_SOC_RESET	BIT(0)
134 
135 #define SYS_WDT4_SW_RESET	BIT(31)
136 #define SYS_WDT4_ARM_RESET	BIT(30)
137 #define SYS_WDT4_FULL_RESET	BIT(29)
138 #define SYS_WDT4_SOC_RESET	BIT(28)
139 #define SYS_WDT3_SW_RESET	BIT(27)
140 #define SYS_WDT3_ARM_RESET	BIT(26)
141 #define SYS_WDT3_FULL_RESET	BIT(25)
142 #define SYS_WDT3_SOC_RESET	BIT(24)
143 #define SYS_WDT2_SW_RESET	BIT(23)
144 #define SYS_WDT2_ARM_RESET	BIT(22)
145 #define SYS_WDT2_FULL_RESET	BIT(21)
146 #define SYS_WDT2_SOC_RESET	BIT(20)
147 #define SYS_WDT1_SW_RESET	BIT(19)
148 #define SYS_WDT1_ARM_RESET	BIT(18)
149 #define SYS_WDT1_FULL_RESET	BIT(17)
150 #define SYS_WDT1_SOC_RESET	BIT(16)
151 
152 #define SYS_CM3_EXT_RESET	BIT(6)
153 #define SYS_PCI2_RESET		BIT(5)
154 #define SYS_PCI1_RESET		BIT(4)
155 #define SYS_DRAM_ECC_RESET	BIT(3)
156 #define SYS_FLASH_ABR_RESET	BIT(2)
157 #define SYS_EXT_RESET		BIT(1)
158 #define SYS_PWR_RESET_FLAG	BIT(0)
159 
160 #define BIT_WDT_SOC(x)	SYS_WDT ## x ## _SOC_RESET
161 #define BIT_WDT_FULL(x)	SYS_WDT ## x ## _FULL_RESET
162 #define BIT_WDT_ARM(x)	SYS_WDT ## x ## _ARM_RESET
163 #define BIT_WDT_SW(x)	SYS_WDT ## x ## _SW_RESET
164 
165 #define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \
166 	if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \
167 		printf("RST: WDT%d ", x); \
168 		if (event_log & BIT_WDT_SOC(x)) { \
169 			printf("SOC "); \
170 			writel(BIT_WDT_SOC(x), event_log_reg); \
171 		} \
172 		if (event_log & BIT_WDT_FULL(x)) { \
173 			printf("FULL "); \
174 			writel(BIT_WDT_FULL(x), event_log_reg); \
175 		} \
176 		if (event_log & BIT_WDT_ARM(x)) { \
177 			printf("ARM "); \
178 			writel(BIT_WDT_ARM(x), event_log_reg); \
179 		} \
180 		if (event_log & BIT_WDT_SW(x)) { \
181 			printf("SW "); \
182 			writel(BIT_WDT_SW(x), event_log_reg); \
183 		} \
184 		printf("\n"); \
185 	} \
186 	(void)(x)
187 
188 void aspeed_print_sysrst_info(void)
189 {
190 	u32 rest = readl(ASPEED_SYS_RESET_CTRL);
191 	u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3);
192 
193 	if (rest & SYS_PWR_RESET_FLAG) {
194 		printf("RST: Power On \n");
195 		writel(rest, ASPEED_SYS_RESET_CTRL);
196 	} else {
197 		HANDLE_WDTx_RESET(8, rest3, ASPEED_SYS_RESET_CTRL3);
198 		HANDLE_WDTx_RESET(7, rest3, ASPEED_SYS_RESET_CTRL3);
199 		HANDLE_WDTx_RESET(6, rest3, ASPEED_SYS_RESET_CTRL3);
200 		HANDLE_WDTx_RESET(5, rest3, ASPEED_SYS_RESET_CTRL3);
201 		HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL);
202 		HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL);
203 		HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL);
204 		HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL);
205 
206 		if (rest & SYS_CM3_EXT_RESET) {
207 			printf("RST: SYS_CM3_EXT_RESET \n");
208 			writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL);
209 		}
210 
211 		if (rest & (SYS_PCI1_RESET | SYS_PCI2_RESET)) {
212 			printf("PCI RST: ");
213 			if (rest & SYS_PCI1_RESET) {
214 				printf("#1 ");
215 				writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL);
216 			}
217 
218 			if (rest & SYS_PCI2_RESET) {
219 				printf("#2 ");
220 				writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL);
221 			}
222 			printf("\n");
223 		}
224 
225 		if (rest & SYS_DRAM_ECC_RESET) {
226 			printf("RST: DRAM_ECC_RESET \n");
227 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
228 		}
229 
230 		if (rest & SYS_FLASH_ABR_RESET) {
231 			printf("RST: SYS_FLASH_ABR_RESET \n");
232 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
233 		}
234 		if (rest & SYS_EXT_RESET) {
235 			printf("RST: External \n");
236 			writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL);
237 		}
238 	}
239 }
240 
241 #define SOC_FW_INIT_DRAM		BIT(7)
242 
243 void aspeed_print_dram_initializer(void)
244 {
245 	if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM)
246 		printf("[init by SOC]\n");
247 	else
248 		printf("[init by VBIOS]\n");
249 }
250 
251 void aspeed_print_2nd_wdt_mode(void)
252 {
253 	if(readl(ASPEED_HW_STRAP2) & BIT(11)) {
254 		printf("2nd Boot: Enable, ");
255 		if(readl(ASPEED_HW_STRAP2) & BIT(12))
256 			printf("Single SPI ");
257 		else
258 			printf("Dual SPI ");
259 		printf(": %s", readl(0x1e620064) & BIT(4) ? "Alternate":"Primary");
260 
261 		if(readl(ASPEED_HW_STRAP2) & GENMASK(15, 13)) {
262 			printf(", bspi_size : %ld MB\n", BIT((readl(ASPEED_HW_STRAP2) >> 13) & 0x7));
263 		} else
264 			printf("\n");
265 	}
266 
267 	if(readl(ASPEED_HW_STRAP2) & BIT(22)) {
268 		printf("SPI aux control : Enable");
269 		//gpioY6 : BSPI_ABR
270 		if (readl(0x1e7801e0) & BIT(6))
271 			printf(", Force Alt boot ");
272 
273 		//gpioY7 : BSPI_WP_N
274 		printf(", BSPI_WP : %s \n", readl(0x1e7801e0) & BIT(7) ? "Disable":"Enable");
275 	}
276 }
277 
278 void aspeed_print_spi_strap_mode(void)
279 {
280 	if(readl(ASPEED_HW_STRAP2) & BIT(10))
281 		printf("SPI: 3/4 byte mode auto detection \n");
282 }
283 
284 void aspeed_print_espi_mode(void)
285 {
286 	int espi_mode = 0;
287 	int sio_disable = 0;
288 	u32 sio_addr = 0x2e;
289 
290 	if (readl(ASPEED_HW_STRAP2) & BIT(6))
291 		espi_mode = 0;
292 	else
293 		espi_mode = 1;
294 
295 	if (readl(ASPEED_HW_STRAP2) & BIT(2))
296 		sio_addr = 0x4e;
297 
298 	if (readl(ASPEED_HW_STRAP2) & BIT(3))
299 		sio_disable = 1;
300 
301 	if (espi_mode)
302 		printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
303 	else
304 		printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
305 
306 	if (!sio_disable)
307 		printf(": SuperIO-%02x\n", sio_addr);
308 	else
309 		printf("\n");
310 }
311 
312 void aspeed_print_mac_info(void)
313 {
314 	int i;
315 	printf("Eth: ");
316 	for (i = 0; i < ASPEED_MAC_COUNT; i++) {
317 		printf("MAC%d: %s", i,
318 				aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI");
319 		if (i != (ASPEED_MAC_COUNT -1))
320 			printf(", ");
321 	}
322 	printf("\n");
323 }
324