1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <asm/io.h> 10 #include <asm/arch/aspeed_scu_info.h> 11 12 /* SoC mapping Table */ 13 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, } 14 15 struct soc_id { 16 const char *name; 17 u32 rev_id; 18 }; 19 20 static struct soc_id soc_map_table[] = { 21 SOC_ID("AST1100/AST2050-A0", 0x00000200), 22 SOC_ID("AST1100/AST2050-A1", 0x00000201), 23 SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202), 24 SOC_ID("AST1510/AST2100-A0", 0x00000300), 25 SOC_ID("AST1510/AST2100-A1", 0x00000301), 26 SOC_ID("AST1510/AST2100-A2,3", 0x00000302), 27 SOC_ID("AST2200-A0,1", 0x00000102), 28 SOC_ID("AST2300-A0", 0x01000003), 29 SOC_ID("AST2300-A1", 0x01010303), 30 SOC_ID("AST1300-A1", 0x01010003), 31 SOC_ID("AST1050-A1", 0x01010203), 32 SOC_ID("AST2400-A0", 0x02000303), 33 SOC_ID("AST2400-A1", 0x02010303), 34 SOC_ID("AST1010-A0", 0x03000003), 35 SOC_ID("AST1010-A1", 0x03010003), 36 SOC_ID("AST3200-A0", 0x04002003), 37 SOC_ID("AST3200-A1", 0x04012003), 38 SOC_ID("AST3200-A2", 0x04032003), 39 SOC_ID("AST1520-A0", 0x03000203), 40 SOC_ID("AST1520-A1", 0x03010203), 41 SOC_ID("AST2510-A0", 0x04000103), 42 SOC_ID("AST2510-A1", 0x04010103), 43 SOC_ID("AST2510-A2", 0x04030103), 44 SOC_ID("AST2520-A0", 0x04000203), 45 SOC_ID("AST2520-A1", 0x04010203), 46 SOC_ID("AST2520-A2", 0x04030203), 47 SOC_ID("AST2500-A0", 0x04000303), 48 SOC_ID("AST2500-A1", 0x04010303), 49 SOC_ID("AST2500-A2", 0x04030303), 50 SOC_ID("AST2530-A0", 0x04000403), 51 SOC_ID("AST2530-A1", 0x04010403), 52 SOC_ID("AST2530-A2", 0x04030403), 53 SOC_ID("AST2600-A0", 0x05000303), 54 SOC_ID("AST2600-A1", 0x05010303), 55 SOC_ID("AST2620-A1", 0x05010203), 56 SOC_ID("AST2600-A2", 0x05020303), 57 SOC_ID("AST2620-A2", 0x05020203), 58 }; 59 60 void aspeed_print_soc_id(void) 61 { 62 int i; 63 u32 rev_id = readl(ASPEED_REVISION_ID); 64 for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { 65 if (rev_id == soc_map_table[i].rev_id) 66 break; 67 } 68 if (i == ARRAY_SIZE(soc_map_table)) 69 printf("UnKnow-SOC: %x \n",rev_id); 70 else 71 printf("SOC: %4s \n",soc_map_table[i].name); 72 } 73 74 int aspeed_get_mac_phy_interface(u8 num) 75 { 76 u32 strap1 = readl(ASPEED_HW_STRAP1); 77 #ifdef ASPEED_HW_STRAP2 78 u32 strap2 = readl(ASPEED_HW_STRAP2); 79 #endif 80 switch(num) { 81 case 0: 82 if(strap1 & BIT(6)) { 83 return 1; 84 } else { 85 return 0; 86 } 87 break; 88 case 1: 89 if(strap1 & BIT(7)) { 90 return 1; 91 } else { 92 return 0; 93 } 94 break; 95 #ifdef ASPEED_HW_STRAP2 96 case 2: 97 if(strap2 & BIT(0)) { 98 return 1; 99 } else { 100 return 0; 101 } 102 break; 103 case 3: 104 if(strap2 & BIT(1)) { 105 return 1; 106 } else { 107 return 0; 108 } 109 break; 110 #endif 111 } 112 return -1; 113 } 114 115 void aspeed_print_security_info(void) 116 { 117 if(readl(ASPEED_HW_STRAP1) & BIT(1)) 118 printf("Security Boot \n"); 119 } 120 121 /* ASPEED_SYS_RESET_CTRL : System reset contrl/status register*/ 122 #define SYS_WDT8_SW_RESET BIT(15) 123 #define SYS_WDT8_ARM_RESET BIT(14) 124 #define SYS_WDT8_FULL_RESET BIT(13) 125 #define SYS_WDT8_SOC_RESET BIT(12) 126 #define SYS_WDT7_SW_RESET BIT(11) 127 #define SYS_WDT7_ARM_RESET BIT(10) 128 #define SYS_WDT7_FULL_RESET BIT(9) 129 #define SYS_WDT7_SOC_RESET BIT(8) 130 #define SYS_WDT6_SW_RESET BIT(7) 131 #define SYS_WDT6_ARM_RESET BIT(6) 132 #define SYS_WDT6_FULL_RESET BIT(5) 133 #define SYS_WDT6_SOC_RESET BIT(4) 134 #define SYS_WDT5_SW_RESET BIT(3) 135 #define SYS_WDT5_ARM_RESET BIT(2) 136 #define SYS_WDT5_FULL_RESET BIT(1) 137 #define SYS_WDT5_SOC_RESET BIT(0) 138 139 #define SYS_WDT4_SW_RESET BIT(31) 140 #define SYS_WDT4_ARM_RESET BIT(30) 141 #define SYS_WDT4_FULL_RESET BIT(29) 142 #define SYS_WDT4_SOC_RESET BIT(28) 143 #define SYS_WDT3_SW_RESET BIT(27) 144 #define SYS_WDT3_ARM_RESET BIT(26) 145 #define SYS_WDT3_FULL_RESET BIT(25) 146 #define SYS_WDT3_SOC_RESET BIT(24) 147 #define SYS_WDT2_SW_RESET BIT(23) 148 #define SYS_WDT2_ARM_RESET BIT(22) 149 #define SYS_WDT2_FULL_RESET BIT(21) 150 #define SYS_WDT2_SOC_RESET BIT(20) 151 #define SYS_WDT1_SW_RESET BIT(19) 152 #define SYS_WDT1_ARM_RESET BIT(18) 153 #define SYS_WDT1_FULL_RESET BIT(17) 154 #define SYS_WDT1_SOC_RESET BIT(16) 155 156 #define SYS_CM3_EXT_RESET BIT(6) 157 #define SYS_PCI2_RESET BIT(5) 158 #define SYS_PCI1_RESET BIT(4) 159 #define SYS_DRAM_ECC_RESET BIT(3) 160 #define SYS_FLASH_ABR_RESET BIT(2) 161 #define SYS_EXT_RESET BIT(1) 162 #define SYS_PWR_RESET_FLAG BIT(0) 163 164 #define BIT_WDT_SOC(x) SYS_WDT ## x ## _SOC_RESET 165 #define BIT_WDT_FULL(x) SYS_WDT ## x ## _FULL_RESET 166 #define BIT_WDT_ARM(x) SYS_WDT ## x ## _ARM_RESET 167 #define BIT_WDT_SW(x) SYS_WDT ## x ## _SW_RESET 168 169 #define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \ 170 if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \ 171 printf("RST: WDT%d ", x); \ 172 if (event_log & BIT_WDT_SOC(x)) { \ 173 printf("SOC "); \ 174 writel(BIT_WDT_SOC(x), event_log_reg); \ 175 } \ 176 if (event_log & BIT_WDT_FULL(x)) { \ 177 printf("FULL "); \ 178 writel(BIT_WDT_FULL(x), event_log_reg); \ 179 } \ 180 if (event_log & BIT_WDT_ARM(x)) { \ 181 printf("ARM "); \ 182 writel(BIT_WDT_ARM(x), event_log_reg); \ 183 } \ 184 if (event_log & BIT_WDT_SW(x)) { \ 185 printf("SW "); \ 186 writel(BIT_WDT_SW(x), event_log_reg); \ 187 } \ 188 printf("\n"); \ 189 } \ 190 (void)(x) 191 192 void aspeed_print_sysrst_info(void) 193 { 194 u32 rest = readl(ASPEED_SYS_RESET_CTRL); 195 u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3); 196 197 if (rest & SYS_PWR_RESET_FLAG) { 198 printf("RST: Power On \n"); 199 writel(rest, ASPEED_SYS_RESET_CTRL); 200 } else { 201 HANDLE_WDTx_RESET(8, rest3, ASPEED_SYS_RESET_CTRL3); 202 HANDLE_WDTx_RESET(7, rest3, ASPEED_SYS_RESET_CTRL3); 203 HANDLE_WDTx_RESET(6, rest3, ASPEED_SYS_RESET_CTRL3); 204 HANDLE_WDTx_RESET(5, rest3, ASPEED_SYS_RESET_CTRL3); 205 HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL); 206 HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL); 207 HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL); 208 HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL); 209 210 if (rest & SYS_CM3_EXT_RESET) { 211 printf("RST: SYS_CM3_EXT_RESET \n"); 212 writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL); 213 } 214 215 if (rest & (SYS_PCI1_RESET | SYS_PCI2_RESET)) { 216 printf("PCI RST: "); 217 if (rest & SYS_PCI1_RESET) { 218 printf("#1 "); 219 writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL); 220 } 221 222 if (rest & SYS_PCI2_RESET) { 223 printf("#2 "); 224 writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL); 225 } 226 printf("\n"); 227 } 228 229 if (rest & SYS_DRAM_ECC_RESET) { 230 printf("RST: DRAM_ECC_RESET \n"); 231 writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL); 232 } 233 234 if (rest & SYS_FLASH_ABR_RESET) { 235 printf("RST: SYS_FLASH_ABR_RESET \n"); 236 writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL); 237 } 238 if (rest & SYS_EXT_RESET) { 239 printf("RST: External \n"); 240 writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL); 241 } 242 } 243 } 244 245 #define SOC_FW_INIT_DRAM BIT(7) 246 247 void aspeed_print_dram_initializer(void) 248 { 249 if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM) 250 printf("[init by SOC]\n"); 251 else 252 printf("[init by VBIOS]\n"); 253 } 254 255 void aspeed_print_2nd_wdt_mode(void) 256 { 257 258 if (readl(ASPEED_HW_STRAP2) & BIT(11)) { 259 printf("FMC 2nd Boot (ABR): Enable"); 260 if (readl(ASPEED_HW_STRAP2) & BIT(12)) 261 printf(", Single flash"); 262 else 263 printf(", Dual flashes"); 264 265 printf(", Source: %s", \ 266 readl(ASPEED_FMC_WDT2) & BIT(4) ? "Alternate" : "Primary"); 267 268 if (readl(ASPEED_HW_STRAP2) & GENMASK(15, 13)) 269 printf(", bspi_size: %ld MB", \ 270 BIT((readl(ASPEED_HW_STRAP2) >> 13) & 0x7)); 271 272 printf("\n"); 273 } 274 } 275 276 void aspeed_print_fmc_aux_ctrl(void) 277 { 278 279 if (readl(ASPEED_HW_STRAP2) & BIT(22)) { 280 printf("FMC aux control: Enable"); 281 /* gpioY6 : BSPI_ABR */ 282 if (readl(ASPEED_GPIO_YZ_DATA) & BIT(6)) 283 printf(", Force Alt boot"); 284 285 /* gpioY7 : BSPI_WP_N */ 286 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7))) 287 printf(", BSPI_WP: Enable"); 288 289 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)) && \ 290 (readl(ASPEED_HW_STRAP2) & GENMASK(24, 23)) != 0) { 291 printf(", FMC HW CRTM: Enable, size: %ld KB", \ 292 BIT((readl(ASPEED_HW_STRAP2) >> 23) & 0x3) * 128); 293 } 294 295 printf("\n"); 296 } 297 } 298 299 void aspeed_print_spi1_abr_mode(void) 300 { 301 if (readl(ASPEED_HW_STRAP2) & BIT(16)) { 302 printf("SPI1 ABR: Enable"); 303 if(readl(ASPEED_SPI1_BOOT_CTRL) & BIT(6)) 304 printf(", Single flash"); 305 else 306 printf(", Dual flashes"); 307 308 printf(", Source : %s", \ 309 readl(ASPEED_SPI1_BOOT_CTRL) & BIT(4) ? "Alternate" : "Primary"); 310 311 if (readl(ASPEED_SPI1_BOOT_CTRL) & GENMASK(3, 1)) 312 printf(", hspi_size : %ld MB", \ 313 BIT((readl(ASPEED_SPI1_BOOT_CTRL) >> 1) & 0x7)); 314 315 printf("\n"); 316 } 317 318 if (readl(ASPEED_HW_STRAP2) & BIT(17)) { 319 printf("SPI1 select pin: Enable"); 320 /* gpioZ1 : HSPI_ABR */ 321 if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9)) 322 printf(", Force Alt boot"); 323 324 printf("\n"); 325 } 326 } 327 328 void aspeed_print_spi1_aux_ctrl(void) 329 { 330 if (readl(ASPEED_HW_STRAP2) & BIT(27)) { 331 printf("SPI1 aux control: Enable"); 332 /* gpioZ1 : HSPI_ABR */ 333 if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9)) 334 printf(", Force Alt boot"); 335 336 /* gpioZ2: BSPI_WP_N */ 337 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10))) 338 printf(", HPI_WP: Enable"); 339 340 if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)) && \ 341 (readl(ASPEED_HW_STRAP2) & GENMASK(26, 25)) != 0) { 342 printf(", SPI1 HW CRTM: Enable, size: %ld KB", \ 343 BIT((readl(ASPEED_HW_STRAP2) >> 25) & 0x3) * 128); 344 } 345 346 printf("\n"); 347 } 348 } 349 350 void aspeed_print_spi_strap_mode(void) 351 { 352 if(readl(ASPEED_HW_STRAP2) & BIT(10)) 353 printf("SPI: 3/4 byte mode auto detection \n"); 354 } 355 356 void aspeed_print_espi_mode(void) 357 { 358 int espi_mode = 0; 359 int sio_disable = 0; 360 u32 sio_addr = 0x2e; 361 362 if (readl(ASPEED_HW_STRAP2) & BIT(6)) 363 espi_mode = 0; 364 else 365 espi_mode = 1; 366 367 if (readl(ASPEED_HW_STRAP2) & BIT(2)) 368 sio_addr = 0x4e; 369 370 if (readl(ASPEED_HW_STRAP2) & BIT(3)) 371 sio_disable = 1; 372 373 if (espi_mode) 374 printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable"); 375 else 376 printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable"); 377 378 if (!sio_disable) 379 printf(": SuperIO-%02x\n", sio_addr); 380 else 381 printf("\n"); 382 } 383 384 void aspeed_print_mac_info(void) 385 { 386 int i; 387 printf("Eth: "); 388 for (i = 0; i < ASPEED_MAC_COUNT; i++) { 389 printf("MAC%d: %s", i, 390 aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI"); 391 if (i != (ASPEED_MAC_COUNT -1)) 392 printf(", "); 393 } 394 printf("\n"); 395 } 396