1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  * Ryan Chen <ryan_chen@aspeedtech.com>
5  */
6 
7 #include <common.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <asm/arch/aspeed_scu_info.h>
11 
12 /* SoC mapping Table */
13 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, }
14 
15 struct soc_id {
16 	const char *name;
17 	u32	   rev_id;
18 };
19 
20 static struct soc_id soc_map_table[] = {
21 	SOC_ID("AST1100/AST2050-A0", 0x00000200),
22 	SOC_ID("AST1100/AST2050-A1", 0x00000201),
23 	SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202),
24 	SOC_ID("AST1510/AST2100-A0", 0x00000300),
25 	SOC_ID("AST1510/AST2100-A1", 0x00000301),
26 	SOC_ID("AST1510/AST2100-A2,3", 0x00000302),
27 	SOC_ID("AST2200-A0,1", 0x00000102),
28 	SOC_ID("AST2300-A0", 0x01000003),
29 	SOC_ID("AST2300-A1", 0x01010303),
30 	SOC_ID("AST1300-A1", 0x01010003),
31 	SOC_ID("AST1050-A1", 0x01010203),
32 	SOC_ID("AST2400-A0", 0x02000303),
33 	SOC_ID("AST2400-A1", 0x02010303),
34 	SOC_ID("AST1010-A0", 0x03000003),
35 	SOC_ID("AST1010-A1", 0x03010003),
36 	SOC_ID("AST3200-A0", 0x04002003),
37 	SOC_ID("AST3200-A1", 0x04012003),
38 	SOC_ID("AST3200-A2", 0x04032003),
39 	SOC_ID("AST1520-A0", 0x03000203),
40 	SOC_ID("AST1520-A1", 0x03010203),
41 	SOC_ID("AST2510-A0", 0x04000103),
42 	SOC_ID("AST2510-A1", 0x04010103),
43 	SOC_ID("AST2510-A2", 0x04030103),
44 	SOC_ID("AST2520-A0", 0x04000203),
45 	SOC_ID("AST2520-A1", 0x04010203),
46 	SOC_ID("AST2520-A2", 0x04030203),
47 	SOC_ID("AST2500-A0", 0x04000303),
48 	SOC_ID("AST2500-A1", 0x04010303),
49 	SOC_ID("AST2500-A2", 0x04030303),
50 	SOC_ID("AST2530-A0", 0x04000403),
51 	SOC_ID("AST2530-A1", 0x04010403),
52 	SOC_ID("AST2530-A2", 0x04030403),
53 	SOC_ID("AST2600-A0", 0x05000303),
54 	SOC_ID("AST2600-A1", 0x05010303),
55 	SOC_ID("AST2620-A1", 0x05010203),
56 	SOC_ID("AST2600-A2", 0x05020303),
57 	SOC_ID("AST2620-A2", 0x05020203),
58 };
59 
60 void aspeed_print_soc_id(void)
61 {
62 	int i;
63 	u32 rev_id = readl(ASPEED_REVISION_ID);
64 	for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) {
65 		if (rev_id == soc_map_table[i].rev_id)
66 			break;
67 	}
68 	if (i == ARRAY_SIZE(soc_map_table))
69 		printf("UnKnow-SOC: %x \n",rev_id);
70 	else
71 		printf("SOC: %4s \n",soc_map_table[i].name);
72 }
73 
74 int aspeed_get_mac_phy_interface(u8 num)
75 {
76 	u32 strap1 = readl(ASPEED_HW_STRAP1);
77 #ifdef ASPEED_HW_STRAP2
78 	u32 strap2 = readl(ASPEED_HW_STRAP2);
79 #endif
80 	switch(num) {
81 		case 0:
82 			if(strap1 & BIT(6)) {
83 				return 1;
84 			} else {
85 				return 0;
86 			}
87 			break;
88 		case 1:
89 			if(strap1 & BIT(7)) {
90 				return 1;
91 			} else {
92 				return 0;
93 			}
94 			break;
95 #ifdef ASPEED_HW_STRAP2
96 		case 2:
97 			if(strap2 & BIT(0)) {
98 				return 1;
99 			} else {
100 				return 0;
101 			}
102 			break;
103 		case 3:
104 			if(strap2 & BIT(1)) {
105 				return 1;
106 			} else {
107 				return 0;
108 			}
109 			break;
110 #endif
111 	}
112 	return -1;
113 }
114 
115 void aspeed_print_security_info(void)
116 {
117 	u32 qsr = readl(ASPEED_OTP_QSR);
118 	u32 sb_sts = readl(ASPEED_SB_STS);
119 	u32 hash;
120 	u32 rsa;
121 	char alg[20];
122 
123 	if (!(sb_sts & BIT(6)))
124 		return;
125 	printf("Secure Boot: ");
126 	if (qsr & BIT(7)) {
127 		hash = (qsr >> 10) & 3;
128 		rsa = (qsr >> 12) & 3;
129 
130 		if (qsr & BIT(27)) {
131 			sprintf(alg + strlen(alg), "AES_");
132 		}
133 		switch (rsa) {
134 		case 0:
135 			sprintf(alg + strlen(alg), "RSA1024_");
136 			break;
137 		case 1:
138 			sprintf(alg + strlen(alg), "RSA2048_");
139 			break;
140 		case 2:
141 			sprintf(alg + strlen(alg), "RSA3072_");
142 			break;
143 		default:
144 			sprintf(alg + strlen(alg), "RSA4096_");
145 			break;
146 		}
147 		switch (hash) {
148 		case 0:
149 			sprintf(alg + strlen(alg), "SHA224");
150 			break;
151 		case 1:
152 			sprintf(alg + strlen(alg), "SHA256");
153 			break;
154 		case 2:
155 			sprintf(alg + strlen(alg), "SHA384");
156 			break;
157 		default:
158 			sprintf(alg + strlen(alg), "SHA512");
159 			break;
160 		}
161 		printf("Mode_2, %s\n", alg);
162 	} else {
163 		printf("Mode_GCM\n");
164 		return;
165 	}
166 }
167 
168 /*	ASPEED_SYS_RESET_CTRL	: System reset contrl/status register*/
169 #define SYS_WDT8_SW_RESET	BIT(15)
170 #define SYS_WDT8_ARM_RESET	BIT(14)
171 #define SYS_WDT8_FULL_RESET	BIT(13)
172 #define SYS_WDT8_SOC_RESET	BIT(12)
173 #define SYS_WDT7_SW_RESET	BIT(11)
174 #define SYS_WDT7_ARM_RESET	BIT(10)
175 #define SYS_WDT7_FULL_RESET	BIT(9)
176 #define SYS_WDT7_SOC_RESET	BIT(8)
177 #define SYS_WDT6_SW_RESET	BIT(7)
178 #define SYS_WDT6_ARM_RESET	BIT(6)
179 #define SYS_WDT6_FULL_RESET	BIT(5)
180 #define SYS_WDT6_SOC_RESET	BIT(4)
181 #define SYS_WDT5_SW_RESET	BIT(3)
182 #define SYS_WDT5_ARM_RESET	BIT(2)
183 #define SYS_WDT5_FULL_RESET	BIT(1)
184 #define SYS_WDT5_SOC_RESET	BIT(0)
185 
186 #define SYS_WDT4_SW_RESET	BIT(31)
187 #define SYS_WDT4_ARM_RESET	BIT(30)
188 #define SYS_WDT4_FULL_RESET	BIT(29)
189 #define SYS_WDT4_SOC_RESET	BIT(28)
190 #define SYS_WDT3_SW_RESET	BIT(27)
191 #define SYS_WDT3_ARM_RESET	BIT(26)
192 #define SYS_WDT3_FULL_RESET	BIT(25)
193 #define SYS_WDT3_SOC_RESET	BIT(24)
194 #define SYS_WDT2_SW_RESET	BIT(23)
195 #define SYS_WDT2_ARM_RESET	BIT(22)
196 #define SYS_WDT2_FULL_RESET	BIT(21)
197 #define SYS_WDT2_SOC_RESET	BIT(20)
198 #define SYS_WDT1_SW_RESET	BIT(19)
199 #define SYS_WDT1_ARM_RESET	BIT(18)
200 #define SYS_WDT1_FULL_RESET	BIT(17)
201 #define SYS_WDT1_SOC_RESET	BIT(16)
202 
203 #define SYS_CM3_EXT_RESET	BIT(6)
204 #define SYS_PCI2_RESET		BIT(5)
205 #define SYS_PCI1_RESET		BIT(4)
206 #define SYS_DRAM_ECC_RESET	BIT(3)
207 #define SYS_FLASH_ABR_RESET	BIT(2)
208 #define SYS_EXT_RESET		BIT(1)
209 #define SYS_PWR_RESET_FLAG	BIT(0)
210 
211 #define BIT_WDT_SOC(x)	SYS_WDT ## x ## _SOC_RESET
212 #define BIT_WDT_FULL(x)	SYS_WDT ## x ## _FULL_RESET
213 #define BIT_WDT_ARM(x)	SYS_WDT ## x ## _ARM_RESET
214 #define BIT_WDT_SW(x)	SYS_WDT ## x ## _SW_RESET
215 
216 #define HANDLE_WDTx_RESET(x, event_log, event_log_reg) \
217 	if (event_log & (BIT_WDT_SOC(x) | BIT_WDT_FULL(x) | BIT_WDT_ARM(x) | BIT_WDT_SW(x))) { \
218 		printf("RST: WDT%d ", x); \
219 		if (event_log & BIT_WDT_SOC(x)) { \
220 			printf("SOC "); \
221 			writel(BIT_WDT_SOC(x), event_log_reg); \
222 		} \
223 		if (event_log & BIT_WDT_FULL(x)) { \
224 			printf("FULL "); \
225 			writel(BIT_WDT_FULL(x), event_log_reg); \
226 		} \
227 		if (event_log & BIT_WDT_ARM(x)) { \
228 			printf("ARM "); \
229 			writel(BIT_WDT_ARM(x), event_log_reg); \
230 		} \
231 		if (event_log & BIT_WDT_SW(x)) { \
232 			printf("SW "); \
233 			writel(BIT_WDT_SW(x), event_log_reg); \
234 		} \
235 		printf("\n"); \
236 	} \
237 	(void)(x)
238 
239 void aspeed_print_sysrst_info(void)
240 {
241 	u32 rest = readl(ASPEED_SYS_RESET_CTRL);
242 	u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3);
243 
244 	if (rest & SYS_PWR_RESET_FLAG) {
245 		printf("RST: Power On \n");
246 		writel(rest, ASPEED_SYS_RESET_CTRL);
247 	} else {
248 		HANDLE_WDTx_RESET(8, rest3, ASPEED_SYS_RESET_CTRL3);
249 		HANDLE_WDTx_RESET(7, rest3, ASPEED_SYS_RESET_CTRL3);
250 		HANDLE_WDTx_RESET(6, rest3, ASPEED_SYS_RESET_CTRL3);
251 		HANDLE_WDTx_RESET(5, rest3, ASPEED_SYS_RESET_CTRL3);
252 		HANDLE_WDTx_RESET(4, rest, ASPEED_SYS_RESET_CTRL);
253 		HANDLE_WDTx_RESET(3, rest, ASPEED_SYS_RESET_CTRL);
254 		HANDLE_WDTx_RESET(2, rest, ASPEED_SYS_RESET_CTRL);
255 		HANDLE_WDTx_RESET(1, rest, ASPEED_SYS_RESET_CTRL);
256 
257 		if (rest & SYS_CM3_EXT_RESET) {
258 			printf("RST: SYS_CM3_EXT_RESET \n");
259 			writel(SYS_CM3_EXT_RESET, ASPEED_SYS_RESET_CTRL);
260 		}
261 
262 		if (rest & (SYS_PCI1_RESET | SYS_PCI2_RESET)) {
263 			printf("PCI RST: ");
264 			if (rest & SYS_PCI1_RESET) {
265 				printf("#1 ");
266 				writel(SYS_PCI1_RESET, ASPEED_SYS_RESET_CTRL);
267 			}
268 
269 			if (rest & SYS_PCI2_RESET) {
270 				printf("#2 ");
271 				writel(SYS_PCI2_RESET, ASPEED_SYS_RESET_CTRL);
272 			}
273 			printf("\n");
274 		}
275 
276 		if (rest & SYS_DRAM_ECC_RESET) {
277 			printf("RST: DRAM_ECC_RESET \n");
278 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
279 		}
280 
281 		if (rest & SYS_FLASH_ABR_RESET) {
282 			printf("RST: SYS_FLASH_ABR_RESET \n");
283 			writel(SYS_FLASH_ABR_RESET, ASPEED_SYS_RESET_CTRL);
284 		}
285 		if (rest & SYS_EXT_RESET) {
286 			printf("RST: External \n");
287 			writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL);
288 		}
289 	}
290 }
291 
292 #define SOC_FW_INIT_DRAM		BIT(7)
293 
294 void aspeed_print_dram_initializer(void)
295 {
296 	if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM)
297 		printf("[init by SOC]\n");
298 	else
299 		printf("[init by VBIOS]\n");
300 }
301 
302 void aspeed_print_2nd_wdt_mode(void)
303 {
304 
305 	if (readl(ASPEED_HW_STRAP2) & BIT(11)) {
306 		printf("FMC 2nd Boot (ABR): Enable");
307 		if (readl(ASPEED_HW_STRAP2) & BIT(12))
308 			printf(", Single flash");
309 		else
310 			printf(", Dual flashes");
311 
312 		printf(", Source: %s", \
313 				readl(ASPEED_FMC_WDT2) & BIT(4) ? "Alternate" : "Primary");
314 
315 		if (readl(ASPEED_HW_STRAP2) & GENMASK(15, 13))
316 			printf(", bspi_size: %ld MB", \
317 				BIT((readl(ASPEED_HW_STRAP2) >> 13) & 0x7));
318 
319 		printf("\n");
320 	}
321 }
322 
323 void aspeed_print_fmc_aux_ctrl(void)
324 {
325 
326 	if (readl(ASPEED_HW_STRAP2) & BIT(22)) {
327 		printf("FMC aux control: Enable");
328 		/* gpioY6 : BSPI_ABR */
329 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(6))
330 			printf(", Force Alt boot");
331 
332 		/* gpioY7 : BSPI_WP_N */
333 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)))
334 			printf(", BSPI_WP: Enable");
335 
336 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(7)) && \
337 			(readl(ASPEED_HW_STRAP2) & GENMASK(24, 23)) != 0) {
338 			printf(", FMC HW CRTM: Enable, size: %ld KB", \
339 					BIT((readl(ASPEED_HW_STRAP2) >> 23) & 0x3) * 128);
340 		}
341 
342 		printf("\n");
343 	}
344 }
345 
346 void aspeed_print_spi1_abr_mode(void)
347 {
348 	if (readl(ASPEED_HW_STRAP2) & BIT(16)) {
349 		printf("SPI1 ABR: Enable");
350 		if(readl(ASPEED_SPI1_BOOT_CTRL) & BIT(6))
351 			printf(", Single flash");
352 		else
353 			printf(", Dual flashes");
354 
355 		printf(", Source : %s", \
356 				readl(ASPEED_SPI1_BOOT_CTRL) & BIT(4) ? "Alternate" : "Primary");
357 
358 		if (readl(ASPEED_SPI1_BOOT_CTRL) & GENMASK(3, 1))
359 			printf(", hspi_size : %ld MB", \
360 				BIT((readl(ASPEED_SPI1_BOOT_CTRL) >> 1) & 0x7));
361 
362 		printf("\n");
363 	}
364 
365 	if (readl(ASPEED_HW_STRAP2) & BIT(17)) {
366 		printf("SPI1 select pin: Enable");
367 		/* gpioZ1 : HSPI_ABR */
368 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9))
369 			printf(", Force Alt boot");
370 
371 		printf("\n");
372 	}
373 }
374 
375 void aspeed_print_spi1_aux_ctrl(void)
376 {
377 	if (readl(ASPEED_HW_STRAP2) & BIT(27)) {
378 		printf("SPI1 aux control: Enable");
379 		/* gpioZ1 : HSPI_ABR */
380 		if (readl(ASPEED_GPIO_YZ_DATA) & BIT(9))
381 			printf(", Force Alt boot");
382 
383 		/* gpioZ2: BSPI_WP_N */
384 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)))
385 			printf(", HPI_WP: Enable");
386 
387 		if (!(readl(ASPEED_GPIO_YZ_DATA) & BIT(10)) && \
388 			(readl(ASPEED_HW_STRAP2) & GENMASK(26, 25)) != 0) {
389 			printf(", SPI1 HW CRTM: Enable, size: %ld KB", \
390 					BIT((readl(ASPEED_HW_STRAP2) >> 25) & 0x3) * 128);
391 		}
392 
393 		printf("\n");
394 	}
395 }
396 
397 void aspeed_print_spi_strap_mode(void)
398 {
399 	if(readl(ASPEED_HW_STRAP2) & BIT(10))
400 		printf("SPI: 3/4 byte mode auto detection \n");
401 }
402 
403 void aspeed_print_espi_mode(void)
404 {
405 	int espi_mode = 0;
406 	int sio_disable = 0;
407 	u32 sio_addr = 0x2e;
408 
409 	if (readl(ASPEED_HW_STRAP2) & BIT(6))
410 		espi_mode = 0;
411 	else
412 		espi_mode = 1;
413 
414 	if (readl(ASPEED_HW_STRAP2) & BIT(2))
415 		sio_addr = 0x4e;
416 
417 	if (readl(ASPEED_HW_STRAP2) & BIT(3))
418 		sio_disable = 1;
419 
420 	if (espi_mode)
421 		printf("eSPI Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
422 	else
423 		printf("LPC Mode: SIO:%s ", sio_disable ? "Disable" : "Enable");
424 
425 	if (!sio_disable)
426 		printf(": SuperIO-%02x\n", sio_addr);
427 	else
428 		printf("\n");
429 }
430 
431 void aspeed_print_mac_info(void)
432 {
433 	int i;
434 	printf("Eth: ");
435 	for (i = 0; i < ASPEED_MAC_COUNT; i++) {
436 		printf("MAC%d: %s", i,
437 				aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI");
438 		if (i != (ASPEED_MAC_COUNT -1))
439 			printf(", ");
440 	}
441 	printf("\n");
442 }
443