1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Syed Mohammed Khasim <khasim@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef OMAP_MMC_H_ 26 #define OMAP_MMC_H_ 27 28 #include <mmc.h> 29 30 struct hsmmc { 31 #ifndef CONFIG_OMAP34XX 32 unsigned int hl_rev; 33 unsigned int hl_hwinfo; 34 unsigned int hl_sysconfig; 35 unsigned char res0[0xf4]; 36 #endif 37 unsigned char res1[0x10]; 38 unsigned int sysconfig; /* 0x10 */ 39 unsigned int sysstatus; /* 0x14 */ 40 unsigned char res2[0x14]; 41 unsigned int con; /* 0x2C */ 42 unsigned int pwcnt; /* 0x30 */ 43 unsigned int dll; /* 0x34 */ 44 unsigned char res3[0xcc]; 45 unsigned int blk; /* 0x104 */ 46 unsigned int arg; /* 0x108 */ 47 unsigned int cmd; /* 0x10C */ 48 unsigned int rsp10; /* 0x110 */ 49 unsigned int rsp32; /* 0x114 */ 50 unsigned int rsp54; /* 0x118 */ 51 unsigned int rsp76; /* 0x11C */ 52 unsigned int data; /* 0x120 */ 53 unsigned int pstate; /* 0x124 */ 54 unsigned int hctl; /* 0x128 */ 55 unsigned int sysctl; /* 0x12C */ 56 unsigned int stat; /* 0x130 */ 57 unsigned int ie; /* 0x134 */ 58 unsigned char res4[0x4]; 59 unsigned int ac12; /* 0x13C */ 60 unsigned int capa; /* 0x140 */ 61 unsigned int capa2; /* 0x144 */ 62 unsigned char res5[0xc]; 63 unsigned int admaes; /* 0x154 */ 64 unsigned int admasal; /* 0x158 */ 65 }; 66 67 struct omap_hsmmc_plat { 68 struct mmc_config cfg; 69 struct hsmmc *base_addr; 70 struct mmc *mmc; 71 u32 controller_flags; 72 const char *hw_rev; 73 }; 74 75 /* 76 * OMAP HS MMC Bit definitions 77 */ 78 #define MADMA_EN (0x1 << 0) 79 #define MMC_SOFTRESET (0x1 << 1) 80 #define RESETDONE (0x1 << 0) 81 #define NOOPENDRAIN (0x0 << 0) 82 #define OPENDRAIN (0x1 << 0) 83 #define OD (0x1 << 0) 84 #define INIT_NOINIT (0x0 << 1) 85 #define INIT_INITSTREAM (0x1 << 1) 86 #define HR_NOHOSTRESP (0x0 << 2) 87 #define STR_BLOCK (0x0 << 3) 88 #define MODE_FUNC (0x0 << 4) 89 #define DW8_1_4BITMODE (0x0 << 5) 90 #define MIT_CTO (0x0 << 6) 91 #define CDP_ACTIVEHIGH (0x0 << 7) 92 #define WPP_ACTIVEHIGH (0x0 << 8) 93 #define RESERVED_MASK (0x3 << 9) 94 #define CTPL_MMC_SD (0x0 << 11) 95 #define DDR (0x1 << 19) 96 #define DMA_MASTER (0x1 << 20) 97 #define BLEN_512BYTESLEN (0x200 << 0) 98 #define NBLK_STPCNT (0x0 << 16) 99 #define DE_ENABLE (0x1 << 0) 100 #define BCE_ENABLE (0x1 << 1) 101 #define ACEN_ENABLE (0x1 << 2) 102 #define DDIR_OFFSET (4) 103 #define DDIR_MASK (0x1 << 4) 104 #define DDIR_WRITE (0x0 << 4) 105 #define DDIR_READ (0x1 << 4) 106 #define MSBS_SGLEBLK (0x0 << 5) 107 #define MSBS_MULTIBLK (0x1 << 5) 108 #define RSP_TYPE_OFFSET (16) 109 #define RSP_TYPE_MASK (0x3 << 16) 110 #define RSP_TYPE_NORSP (0x0 << 16) 111 #define RSP_TYPE_LGHT136 (0x1 << 16) 112 #define RSP_TYPE_LGHT48 (0x2 << 16) 113 #define RSP_TYPE_LGHT48B (0x3 << 16) 114 #define CCCE_NOCHECK (0x0 << 19) 115 #define CCCE_CHECK (0x1 << 19) 116 #define CICE_NOCHECK (0x0 << 20) 117 #define CICE_CHECK (0x1 << 20) 118 #define DP_OFFSET (21) 119 #define DP_MASK (0x1 << 21) 120 #define DP_NO_DATA (0x0 << 21) 121 #define DP_DATA (0x1 << 21) 122 #define CMD_TYPE_NORMAL (0x0 << 22) 123 #define INDEX_OFFSET (24) 124 #define INDEX_MASK (0x3f << 24) 125 #define INDEX(i) (i << 24) 126 #define DATI_MASK (0x1 << 1) 127 #define CMDI_MASK (0x1 << 0) 128 #define DTW_1_BITMODE (0x0 << 1) 129 #define DTW_4_BITMODE (0x1 << 1) 130 #define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ 131 #define SDBP_PWROFF (0x0 << 8) 132 #define SDBP_PWRON (0x1 << 8) 133 #define SDVS_MASK (0x7 << 9) 134 #define SDVS_1V8 (0x5 << 9) 135 #define SDVS_3V0 (0x6 << 9) 136 #define SDVS_3V3 (0x7 << 9) 137 #define DMA_SELECT (0x2 << 3) 138 #define ICE_MASK (0x1 << 0) 139 #define ICE_STOP (0x0 << 0) 140 #define ICS_MASK (0x1 << 1) 141 #define ICS_NOTREADY (0x0 << 1) 142 #define ICE_OSCILLATE (0x1 << 0) 143 #define CEN_MASK (0x1 << 2) 144 #define CEN_ENABLE (0x1 << 2) 145 #define CLKD_OFFSET (6) 146 #define CLKD_MASK (0x3FF << 6) 147 #define DTO_MASK (0xF << 16) 148 #define DTO_15THDTO (0xE << 16) 149 #define SOFTRESETALL (0x1 << 24) 150 #define CC_MASK (0x1 << 0) 151 #define TC_MASK (0x1 << 1) 152 #define BWR_MASK (0x1 << 4) 153 #define BRR_MASK (0x1 << 5) 154 #define ERRI_MASK (0x1 << 15) 155 #define IE_CC (0x01 << 0) 156 #define IE_TC (0x01 << 1) 157 #define IE_BWR (0x01 << 4) 158 #define IE_BRR (0x01 << 5) 159 #define IE_CTO (0x01 << 16) 160 #define IE_CCRC (0x01 << 17) 161 #define IE_CEB (0x01 << 18) 162 #define IE_CIE (0x01 << 19) 163 #define IE_DTO (0x01 << 20) 164 #define IE_DCRC (0x01 << 21) 165 #define IE_DEB (0x01 << 22) 166 #define IE_ADMAE (0x01 << 25) 167 #define IE_CERR (0x01 << 28) 168 #define IE_BADA (0x01 << 29) 169 170 #define VS33_3V3SUP BIT(24) 171 #define VS30_3V0SUP BIT(25) 172 #define VS18_1V8SUP BIT(26) 173 174 #define AC12_ET BIT(22) 175 #define AC12_V1V8_SIGEN BIT(19) 176 #define AC12_SCLK_SEL BIT(23) 177 #define AC12_UHSMC_MASK (7 << 16) 178 #define AC12_UHSMC_DDR50 (4 << 16) 179 #define AC12_UHSMC_SDR104 (3 << 16) 180 #define AC12_UHSMC_SDR50 (2 << 16) 181 #define AC12_UHSMC_SDR25 (1 << 16) 182 #define AC12_UHSMC_SDR12 (0 << 16) 183 #define AC12_UHSMC_RES (0x7 << 16) 184 185 /* Driver definitions */ 186 #define MMCSD_SECTOR_SIZE 512 187 #define MMC_CARD 0 188 #define SD_CARD 1 189 #define BYTE_MODE 0 190 #define SECTOR_MODE 1 191 #define CLK_INITSEQ 0 192 #define CLK_400KHZ 1 193 #define CLK_MISC 2 194 195 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 196 197 #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) 198 #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) 199 200 /* Clock Configurations and Macros */ 201 #ifdef CONFIG_OMAP54XX 202 #define MMC_CLOCK_REFERENCE 192 /* MHz */ 203 #else 204 #define MMC_CLOCK_REFERENCE 96 /* MHz */ 205 #endif 206 207 /* DLL */ 208 #define DLL_SWT BIT(20) 209 #define DLL_FORCE_SR_C_SHIFT 13 210 #define DLL_FORCE_SR_C_MASK 0x7f 211 #define DLL_FORCE_VALUE BIT(12) 212 #define DLL_CALIB BIT(1) 213 214 #define MAX_PHASE_DELAY 0x7c 215 216 /* CAPA2 */ 217 #define CAPA2_TSDR50 BIT(13) 218 219 #define mmc_reg_out(addr, mask, val)\ 220 writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) 221 222 #define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\ 223 IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\ 224 IE_BRR | IE_BWR | IE_TC | IE_CC) 225 226 #define CON_CLKEXTFREE BIT(16) 227 #define CON_PADEN BIT(15) 228 #define PSTATE_CLEV BIT(24) 229 #define PSTATE_DLEV (0xF << 20) 230 #define PSTATE_DLEV_DAT0 (0x1 << 20) 231 232 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 233 int wp_gpio); 234 235 void vmmc_pbias_config(uint voltage); 236 void board_mmc_poweron_ldo(uint voltage); 237 #endif /* OMAP_MMC_H_ */ 238