1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Syed Mohammed Khasim <khasim@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef OMAP_MMC_H_ 26 #define OMAP_MMC_H_ 27 28 struct hsmmc { 29 #ifdef CONFIG_DM_MMC 30 unsigned char res0[0x100]; 31 #endif 32 unsigned char res1[0x10]; 33 unsigned int sysconfig; /* 0x10 */ 34 unsigned int sysstatus; /* 0x14 */ 35 unsigned char res2[0x14]; 36 unsigned int con; /* 0x2C */ 37 unsigned char res3[0xD4]; 38 unsigned int blk; /* 0x104 */ 39 unsigned int arg; /* 0x108 */ 40 unsigned int cmd; /* 0x10C */ 41 unsigned int rsp10; /* 0x110 */ 42 unsigned int rsp32; /* 0x114 */ 43 unsigned int rsp54; /* 0x118 */ 44 unsigned int rsp76; /* 0x11C */ 45 unsigned int data; /* 0x120 */ 46 unsigned int pstate; /* 0x124 */ 47 unsigned int hctl; /* 0x128 */ 48 unsigned int sysctl; /* 0x12C */ 49 unsigned int stat; /* 0x130 */ 50 unsigned int ie; /* 0x134 */ 51 unsigned char res4[0x8]; 52 unsigned int capa; /* 0x140 */ 53 }; 54 55 /* 56 * OMAP HS MMC Bit definitions 57 */ 58 #define MMC_SOFTRESET (0x1 << 1) 59 #define RESETDONE (0x1 << 0) 60 #define NOOPENDRAIN (0x0 << 0) 61 #define OPENDRAIN (0x1 << 0) 62 #define OD (0x1 << 0) 63 #define INIT_NOINIT (0x0 << 1) 64 #define INIT_INITSTREAM (0x1 << 1) 65 #define HR_NOHOSTRESP (0x0 << 2) 66 #define STR_BLOCK (0x0 << 3) 67 #define MODE_FUNC (0x0 << 4) 68 #define DW8_1_4BITMODE (0x0 << 5) 69 #define MIT_CTO (0x0 << 6) 70 #define CDP_ACTIVEHIGH (0x0 << 7) 71 #define WPP_ACTIVEHIGH (0x0 << 8) 72 #define RESERVED_MASK (0x3 << 9) 73 #define CTPL_MMC_SD (0x0 << 11) 74 #define BLEN_512BYTESLEN (0x200 << 0) 75 #define NBLK_STPCNT (0x0 << 16) 76 #define DE_DISABLE (0x0 << 0) 77 #define BCE_DISABLE (0x0 << 1) 78 #define BCE_ENABLE (0x1 << 1) 79 #define ACEN_DISABLE (0x0 << 2) 80 #define DDIR_OFFSET (4) 81 #define DDIR_MASK (0x1 << 4) 82 #define DDIR_WRITE (0x0 << 4) 83 #define DDIR_READ (0x1 << 4) 84 #define MSBS_SGLEBLK (0x0 << 5) 85 #define MSBS_MULTIBLK (0x1 << 5) 86 #define RSP_TYPE_OFFSET (16) 87 #define RSP_TYPE_MASK (0x3 << 16) 88 #define RSP_TYPE_NORSP (0x0 << 16) 89 #define RSP_TYPE_LGHT136 (0x1 << 16) 90 #define RSP_TYPE_LGHT48 (0x2 << 16) 91 #define RSP_TYPE_LGHT48B (0x3 << 16) 92 #define CCCE_NOCHECK (0x0 << 19) 93 #define CCCE_CHECK (0x1 << 19) 94 #define CICE_NOCHECK (0x0 << 20) 95 #define CICE_CHECK (0x1 << 20) 96 #define DP_OFFSET (21) 97 #define DP_MASK (0x1 << 21) 98 #define DP_NO_DATA (0x0 << 21) 99 #define DP_DATA (0x1 << 21) 100 #define CMD_TYPE_NORMAL (0x0 << 22) 101 #define INDEX_OFFSET (24) 102 #define INDEX_MASK (0x3f << 24) 103 #define INDEX(i) (i << 24) 104 #define DATI_MASK (0x1 << 1) 105 #define CMDI_MASK (0x1 << 0) 106 #define DTW_1_BITMODE (0x0 << 1) 107 #define DTW_4_BITMODE (0x1 << 1) 108 #define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ 109 #define SDBP_PWROFF (0x0 << 8) 110 #define SDBP_PWRON (0x1 << 8) 111 #define SDVS_1V8 (0x5 << 9) 112 #define SDVS_3V0 (0x6 << 9) 113 #define ICE_MASK (0x1 << 0) 114 #define ICE_STOP (0x0 << 0) 115 #define ICS_MASK (0x1 << 1) 116 #define ICS_NOTREADY (0x0 << 1) 117 #define ICE_OSCILLATE (0x1 << 0) 118 #define CEN_MASK (0x1 << 2) 119 #define CEN_DISABLE (0x0 << 2) 120 #define CEN_ENABLE (0x1 << 2) 121 #define CLKD_OFFSET (6) 122 #define CLKD_MASK (0x3FF << 6) 123 #define DTO_MASK (0xF << 16) 124 #define DTO_15THDTO (0xE << 16) 125 #define SOFTRESETALL (0x1 << 24) 126 #define CC_MASK (0x1 << 0) 127 #define TC_MASK (0x1 << 1) 128 #define BWR_MASK (0x1 << 4) 129 #define BRR_MASK (0x1 << 5) 130 #define ERRI_MASK (0x1 << 15) 131 #define IE_CC (0x01 << 0) 132 #define IE_TC (0x01 << 1) 133 #define IE_BWR (0x01 << 4) 134 #define IE_BRR (0x01 << 5) 135 #define IE_CTO (0x01 << 16) 136 #define IE_CCRC (0x01 << 17) 137 #define IE_CEB (0x01 << 18) 138 #define IE_CIE (0x01 << 19) 139 #define IE_DTO (0x01 << 20) 140 #define IE_DCRC (0x01 << 21) 141 #define IE_DEB (0x01 << 22) 142 #define IE_CERR (0x01 << 28) 143 #define IE_BADA (0x01 << 29) 144 145 #define VS30_3V0SUP (1 << 25) 146 #define VS18_1V8SUP (1 << 26) 147 148 /* Driver definitions */ 149 #define MMCSD_SECTOR_SIZE 512 150 #define MMC_CARD 0 151 #define SD_CARD 1 152 #define BYTE_MODE 0 153 #define SECTOR_MODE 1 154 #define CLK_INITSEQ 0 155 #define CLK_400KHZ 1 156 #define CLK_MISC 2 157 158 #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) 159 #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) 160 161 /* Clock Configurations and Macros */ 162 #define MMC_CLOCK_REFERENCE 96 /* MHz */ 163 164 #define mmc_reg_out(addr, mask, val)\ 165 writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) 166 167 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, 168 int wp_gpio); 169 170 void vmmc_pbias_config(uint voltage); 171 #endif /* OMAP_MMC_H_ */ 172