1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Sunxi platform Push-Push i2c register definition.
4  *
5  * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
6  * http://linux-sunxi.org
7  *
8  * (c)Copyright 2006-2013
9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10  * Berg Xing <bergxing@allwinnertech.com>
11  * Tom Cubie <tangliang@allwinnertech.com>
12  */
13 
14 #ifndef _SUNXI_P2WI_H
15 #define _SUNXI_P2WI_H
16 
17 #include <linux/types.h>
18 
19 #define P2WI_CTRL_RESET (0x1 << 0)
20 #define P2WI_CTRL_IRQ_EN (0x1 << 1)
21 #define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
22 #define P2WI_CTRL_TRANS_START (0x1 << 7)
23 
24 #define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
25 #define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
26 #define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
27 #define P2WI_CC_CLK_DIV(n) \
28 	__P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
29 #define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
30 #define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
31 
32 #define P2WI_IRQ_TRANS_DONE (0x1 << 0)
33 #define P2WI_IRQ_TRANS_ERR (0x1 << 1)
34 #define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
35 
36 #define P2WI_STAT_TRANS_DONE (0x1 << 0)
37 #define P2WI_STAT_TRANS_ERR (0x1 << 1)
38 #define P2WI_STAT_LOAD_BUSY (0x1 << 2)
39 #define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
40 #define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
41 #define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
42 #define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
43 #define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
44 #define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
45 #define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
46 #define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
47 #define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
48 #define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
49 #define P2WI_STAT_TRANS_ERR_BYTE_1 \
50 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
51 #define P2WI_STAT_TRANS_ERR_BYTE_2 \
52 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
53 #define P2WI_STAT_TRANS_ERR_BYTE_3 \
54 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
55 #define P2WI_STAT_TRANS_ERR_BYTE_4 \
56 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
57 #define P2WI_STAT_TRANS_ERR_BYTE_5 \
58 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
59 #define P2WI_STAT_TRANS_ERR_BYTE_6 \
60 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
61 #define P2WI_STAT_TRANS_ERR_BYTE_7 \
62 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
63 #define P2WI_STAT_TRANS_ERR_BYTE_8 \
64 	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
65 
66 #define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
67 #define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
68 #define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
69 #define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
70 #define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
71 #define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
72 #define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
73 #define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
74 #define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
75 #define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
76 #define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
77 #define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
78 #define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
79 #define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
80 #define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
81 #define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
82 
83 #define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
84 #define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
85 #define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
86 #define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
87 
88 #define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
89 #define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
90 #define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
91 #define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
92 #define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
93 #define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
94 #define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
95 #define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
96 #define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
97 #define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
98 #define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
99 #define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
100 #define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
101 #define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
102 #define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
103 #define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
104 
105 #define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
106 #define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
107 #define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
108 #define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
109 #define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
110 #define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
111 
112 #define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
113 #define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
114 #define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
115 #define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
116 #define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
117 #define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
118 #define P2WI_PM_INIT_SEND (0x1 << 31)
119 
120 struct sunxi_p2wi_reg {
121 	u32 ctrl;	/* 0x00 control */
122 	u32 cc;		/* 0x04 clock control */
123 	u32 irq;	/* 0x08 interrupt */
124 	u32 status;	/* 0x0c status */
125 	u32 dataddr0;	/* 0x10 data address 0 */
126 	u32 dataddr1;	/* 0x14 data address 1 */
127 	u32 numbytes;	/* 0x18 num bytes */
128 	u32 data0;	/* 0x1c data buffer 0 */
129 	u32 data1;	/* 0x20 data buffer 1 */
130 	u32 linectrl;	/* 0x24 line control */
131 	u32 pm;		/* 0x28 power management */
132 };
133 
134 void p2wi_init(void);
135 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
136 int p2wi_read(const u8 addr, u8 *data);
137 int p2wi_write(const u8 addr, u8 data);
138 
139 #endif /* _SUNXI_P2WI_H */
140