1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #ifndef _ASM_ARCH_SDRAM_AST2600_H 6 #define _ASM_ARCH_SDRAM_AST2600_H 7 8 /* keys for unlocking HW */ 9 #define SDRAM_UNLOCK_KEY 0xFC600309 10 #define SDRAM_VIDEO_UNLOCK_KEY 0x0044000B 11 12 /* Fixed priority DRAM Requests mask */ 13 #define REQ_PRI_VGA_HW_CURSOR_R 0 14 #define REQ_PRI_VGA_CRT_R 1 15 #define REQ_PRI_SOC_DISPLAY_CTRL_R 2 16 #define REQ_PRI_PCIE_BUS1_RW 3 17 #define REQ_PRI_VIDEO_HIGH_PRI_W 4 18 #define REQ_PRI_CPU_RW 5 19 #define REQ_PRI_SLI_RW 6 20 #define REQ_PRI_PCIE_BUS2_RW 7 21 #define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8 22 #define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9 23 #define REQ_PRI_USB1_1_UHCI_HOST_RW 10 24 #define REQ_PRI_AHB_BUS_RW 11 25 #define REQ_PRI_CM3_DATA_RW 12 26 #define REQ_PRI_CM3_INST_R 13 27 #define REQ_PRI_MAC0_DMA_RW 14 28 #define REQ_PRI_MAC1_DMA_RW 15 29 #define REQ_PRI_SDIO_DMA_RW 16 30 #define REQ_PRI_PILOT_ENGINE_RW 17 31 #define REQ_PRI_XDMA1_RW 18 32 #define REQ_PRI_MCTP1_RW 19 33 #define REQ_PRI_VIDEO_FLAG_RW 20 34 #define REQ_PRI_VIDEO_LOW_PRI_W 21 35 #define REQ_PRI_2D_ENGINE_DATA_RW 22 36 #define REQ_PRI_ENC_ENGINE_RW 23 37 #define REQ_PRI_MCTP2_RW 24 38 #define REQ_PRI_XDMA2_RW 25 39 #define REQ_PRI_ECC_RSA_RW 26 40 41 #define MCR30_RESET_DLL_DELAY_EN BIT(4) 42 #define MCR30_MODE_REG_SEL_SHIFT 1 43 #define MCR30_MODE_REG_SEL_MASK (0x7 << MCR30_MODE_REG_SEL_SHIFT) 44 #define MCR30_SET_MODE_REG BIT(0) 45 46 #define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_MASK) | MCR30_SET_MODE_REG) 47 48 #define MCR34_CURR_CKE_OUT_VAL (0x1 << 31) 49 #define MCR34_SELF_REFRESH_STATUS_SHIFT 28 50 #define MCR34_SELF_REFRESH_STATUS_MASK (0x7 << MCR34_SELF_REFRESH_STATUS_SHIFT) 51 52 #define MCR34_ODT_DELAY_SHIFT 12 53 #define MCR34_ODT_DELAY_MASK (0xF << MCR34_ODT_DELAY_SHIFT) 54 #define MCR34_ODT_EXT_SHIFT 10 55 #define MCR34_ODT_EXT_MASK (0x3 << MCR34_ODT_EXT_SHIFT) 56 #define MCR34_ODT_AUTO_ON (0x1 << 9) 57 #define MCR34_ODT_EN (0x1 << 8) 58 #define MCR34_RESETN_DIS (0x1 << 7) 59 #define MCR34_MREQI_DIS (0x1 << 6) 60 #define MCR34_MREQ_BYPASS_DIS (0x1 << 5) 61 #define MCR34_RGAP_CTRL_EN (0x1 << 4) 62 #define MCR34_CKE_OUT_IN_SELF_REF_DIS (0x1 << 3) 63 #define MCR34_FOURCE_SELF_REF_EN (0x1 << 2) 64 #define MCR34_AUTOPWRDN_EN (0x1 << 1) 65 #define MCR34_CKE_EN (0x1 << 0) 66 67 #define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT 16 68 #define MCR38_RW_MAX_GRANT_CNT_RQ_MASK (0x1F << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT) 69 70 /* default request queued limitation mask (0xFFBBFFF4) */ 71 #define MCR3C_DEFAULT_MASK \ 72 ~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \ 73 REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW) 74 75 #define MCR50_RESET_ALL_INTR (1 << 31) 76 77 #define SDRAM_CONF_SCRAMBLE (0x1 << 8) 78 #define SDRAM_CONF_ECC_EN (0x1 << 7) 79 #define SDRAM_CONF_DUALX8 (0x1 << 5) 80 #define SDRAM_CONF_DDR4 (0x1 << 4) 81 #define SDRAM_CONF_VGA_SIZE_SHIFT 2 82 #define SDRAM_CONF_VGA_SIZE_MASK (0x3 << SDRAM_CONF_VGA_SIZE_MASK) 83 #define SDRAM_CONF_CAP_SHIFT 0 84 #define SDRAM_CONF_CAP_MASK (0x3 << SDRAM_CONF_CAP_SHIFT) 85 86 #define SDRAM_CONF_CAP_256M 0 87 #define SDRAM_CONF_CAP_512M 1 88 #define SDRAM_CONF_CAP_1024M 2 89 #define SDRAM_CONF_CAP_2048M 3 90 91 #define SDRAM_MISC_DDR4_TREFRESH (1 << 3) 92 93 #define SDRAM_PHYCTRL0_PLL_LOCKED BIT(4) 94 #define SDRAM_PHYCTRL0_NRST BIT(2) 95 #define SDRAM_PHYCTRL0_INIT BIT(0) 96 97 #define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT 16 98 #define SDRAM_REFRESH_PERIOD_ZQCS_MASK (0xffff << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT) 99 #define SDRAM_REFRESH_PERIOD_SHIFT 8 100 #define SDRAM_REFRESH_PERIOD_MASK (0xff << SDRAM_REFRESH_PERIOD_SHIFT) 101 #define SDRAM_REFRESH_ZQCS_EN BIT(7) 102 #define SDRAM_RESET_DLL_ZQCL_EN BIT(6) 103 #define SDRAM_LOW_PRI_REFRESH_EN BIT(5) 104 #define SDRAM_FORCE_PRECHARGE_EN BIT(4) 105 #define SDRAM_REFRESH_EN BIT(0) 106 107 #define SDRAM_TEST_LEN_SHIFT 4 108 #define SDRAM_TEST_LEN_MASK 0xfffff 109 #define SDRAM_TEST_START_ADDR_SHIFT 24 110 #define SDRAM_TEST_START_ADDR_MASK 0x3f 111 112 #define SDRAM_TEST_EN (1 << 0) 113 #define SDRAM_TEST_MODE_SHIFT 1 114 #define SDRAM_TEST_MODE_MASK 3 115 #define SDRAM_TEST_MODE_WO 0 116 #define SDRAM_TEST_MODE_RB 1 117 #define SDRAM_TEST_MODE_RW 2 118 #define SDRAM_TEST_GEN_MODE_SHIFT 3 119 #define SDRAM_TEST_GEN_MODE_MASK 7 120 #define SDRAM_TEST_TWO_MODES (1 << 6) 121 #define SDRAM_TEST_ERRSTOP (1 << 7) 122 #define SDRAM_TEST_DONE (1 << 12) 123 #define SDRAM_TEST_FAIL (1 << 13) 124 125 #define SDRAM_AC_TRFC_SHIFT 0 126 #define SDRAM_AC_TRFC_MASK 0xff 127 128 #ifndef __ASSEMBLY__ 129 130 struct ast2600_sdrammc_regs { 131 u32 protection_key; /* offset 0x00 */ 132 u32 config; /* offset 0x04 */ 133 u32 gm_protection_key; /* offset 0x08 */ 134 u32 refresh_timing; /* offset 0x0C */ 135 u32 ac_timing[4]; /* offset 0x10 ~ 0x1C */ 136 u32 mr01_mode_setting; /* offset 0x20 */ 137 u32 mr23_mode_setting; /* offset 0x24 */ 138 u32 mr45_mode_setting; /* offset 0x28 */ 139 u32 mr6_mode_setting; /* offset 0x2C */ 140 u32 mode_setting_control; /* offset 0x30 */ 141 u32 power_ctrl; /* offset 0x34 */ 142 u32 arbitration_ctrl; /* offset 0x38 */ 143 u32 req_limit_mask; /* offset 0x3C */ 144 u32 max_grant_len[4]; /* offset 0x40 ~ 0x4C */ 145 u32 intr_ctrl; /* offset 0x50 */ 146 u32 ecc_range_ctrl; /* offset 0x54 */ 147 u32 first_ecc_err_addr; /* offset 0x58 */ 148 u32 last_ecc_err_addr; /* offset 0x5C */ 149 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ 150 u32 ecc_test_ctrl; /* offset 0x70 */ 151 u32 test_addr; /* offset 0x74 */ 152 u32 test_fail_dq_bit; /* offset 0x78 */ 153 u32 test_init_val; /* offset 0x7C */ 154 u32 req_input_ctrl; /* offset 0x80 */ 155 u32 req_high_pri_ctrl; /* offset 0x84 */ 156 157 u32 phy_debug_ctrl; 158 u32 phy_debug_data; 159 u32 reserved1[30]; 160 u32 scu_passwd; 161 u32 reserved2[7]; 162 u32 scu_mpll; 163 u32 reserved3[19]; 164 u32 scu_hwstrap; 165 }; 166 167 #endif /* __ASSEMBLY__ */ 168 169 #endif /* _ASM_ARCH_SDRAM_AST2600_H */ 170