1/* 2 * dts file for Xilinx ZynqMP 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/ { 12 compatible = "xlnx,zynqmp"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 operating-points-v2 = <&cpu_opp_table>; 25 reg = <0x0>; 26 cpu-idle-states = <&CPU_SLEEP_0>; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a53", "arm,armv8"; 31 device_type = "cpu"; 32 enable-method = "psci"; 33 reg = <0x1>; 34 operating-points-v2 = <&cpu_opp_table>; 35 cpu-idle-states = <&CPU_SLEEP_0>; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 reg = <0x2>; 43 operating-points-v2 = <&cpu_opp_table>; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 }; 46 47 cpu3: cpu@3 { 48 compatible = "arm,cortex-a53", "arm,armv8"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x3>; 52 operating-points-v2 = <&cpu_opp_table>; 53 cpu-idle-states = <&CPU_SLEEP_0>; 54 }; 55 56 idle-states { 57 entry-method = "arm,psci"; 58 59 CPU_SLEEP_0: cpu-sleep-0 { 60 compatible = "arm,idle-state"; 61 arm,psci-suspend-param = <0x40000000>; 62 local-timer-stop; 63 entry-latency-us = <300>; 64 exit-latency-us = <600>; 65 min-residency-us = <10000>; 66 }; 67 }; 68 }; 69 70 cpu_opp_table: cpu_opp_table { 71 compatible = "operating-points-v2"; 72 opp-shared; 73 opp00 { 74 opp-hz = /bits/ 64 <1199999988>; 75 opp-microvolt = <1000000>; 76 clock-latency-ns = <500000>; 77 }; 78 opp01 { 79 opp-hz = /bits/ 64 <599999994>; 80 opp-microvolt = <1000000>; 81 clock-latency-ns = <500000>; 82 }; 83 opp02 { 84 opp-hz = /bits/ 64 <399999996>; 85 opp-microvolt = <1000000>; 86 clock-latency-ns = <500000>; 87 }; 88 opp03 { 89 opp-hz = /bits/ 64 <299999997>; 90 opp-microvolt = <1000000>; 91 clock-latency-ns = <500000>; 92 }; 93 }; 94 95 dcc: dcc { 96 compatible = "arm,dcc"; 97 status = "disabled"; 98 u-boot,dm-pre-reloc; 99 }; 100 101 power-domains { 102 compatible = "xlnx,zynqmp-genpd"; 103 104 pd_usb0: pd-usb0 { 105 #power-domain-cells = <0x0>; 106 pd-id = <0x16>; 107 }; 108 109 pd_usb1: pd-usb1 { 110 #power-domain-cells = <0x0>; 111 pd-id = <0x17>; 112 }; 113 114 pd_sata: pd-sata { 115 #power-domain-cells = <0x0>; 116 pd-id = <0x1c>; 117 }; 118 119 pd_spi0: pd-spi0 { 120 #power-domain-cells = <0x0>; 121 pd-id = <0x23>; 122 }; 123 124 pd_spi1: pd-spi1 { 125 #power-domain-cells = <0x0>; 126 pd-id = <0x24>; 127 }; 128 129 pd_uart0: pd-uart0 { 130 #power-domain-cells = <0x0>; 131 pd-id = <0x21>; 132 }; 133 134 pd_uart1: pd-uart1 { 135 #power-domain-cells = <0x0>; 136 pd-id = <0x22>; 137 }; 138 139 pd_eth0: pd-eth0 { 140 #power-domain-cells = <0x0>; 141 pd-id = <0x1d>; 142 }; 143 144 pd_eth1: pd-eth1 { 145 #power-domain-cells = <0x0>; 146 pd-id = <0x1e>; 147 }; 148 149 pd_eth2: pd-eth2 { 150 #power-domain-cells = <0x0>; 151 pd-id = <0x1f>; 152 }; 153 154 pd_eth3: pd-eth3 { 155 #power-domain-cells = <0x0>; 156 pd-id = <0x20>; 157 }; 158 159 pd_i2c0: pd-i2c0 { 160 #power-domain-cells = <0x0>; 161 pd-id = <0x25>; 162 }; 163 164 pd_i2c1: pd-i2c1 { 165 #power-domain-cells = <0x0>; 166 pd-id = <0x26>; 167 }; 168 169 pd_dp: pd-dp { 170 #power-domain-cells = <0x0>; 171 pd-id = <0x29>; 172 }; 173 174 pd_gdma: pd-gdma { 175 #power-domain-cells = <0x0>; 176 pd-id = <0x2a>; 177 }; 178 179 pd_adma: pd-adma { 180 #power-domain-cells = <0x0>; 181 pd-id = <0x2b>; 182 }; 183 184 pd_ttc0: pd-ttc0 { 185 #power-domain-cells = <0x0>; 186 pd-id = <0x18>; 187 }; 188 189 pd_ttc1: pd-ttc1 { 190 #power-domain-cells = <0x0>; 191 pd-id = <0x19>; 192 }; 193 194 pd_ttc2: pd-ttc2 { 195 #power-domain-cells = <0x0>; 196 pd-id = <0x1a>; 197 }; 198 199 pd_ttc3: pd-ttc3 { 200 #power-domain-cells = <0x0>; 201 pd-id = <0x1b>; 202 }; 203 204 pd_sd0: pd-sd0 { 205 #power-domain-cells = <0x0>; 206 pd-id = <0x27>; 207 }; 208 209 pd_sd1: pd-sd1 { 210 #power-domain-cells = <0x0>; 211 pd-id = <0x28>; 212 }; 213 214 pd_nand: pd-nand { 215 #power-domain-cells = <0x0>; 216 pd-id = <0x2c>; 217 }; 218 219 pd_qspi: pd-qspi { 220 #power-domain-cells = <0x0>; 221 pd-id = <0x2d>; 222 }; 223 224 pd_gpio: pd-gpio { 225 #power-domain-cells = <0x0>; 226 pd-id = <0x2e>; 227 }; 228 229 pd_can0: pd-can0 { 230 #power-domain-cells = <0x0>; 231 pd-id = <0x2f>; 232 }; 233 234 pd_can1: pd-can1 { 235 #power-domain-cells = <0x0>; 236 pd-id = <0x30>; 237 }; 238 239 pd_pcie: pd-pcie { 240 #power-domain-cells = <0x0>; 241 pd-id = <0x3b>; 242 }; 243 244 pd_gpu: pd-gpu { 245 #power-domain-cells = <0x0>; 246 pd-id = <0x3a 0x14 0x15>; 247 }; 248 }; 249 250 pmu { 251 compatible = "arm,armv8-pmuv3"; 252 interrupt-parent = <&gic>; 253 interrupts = <0 143 4>, 254 <0 144 4>, 255 <0 145 4>, 256 <0 146 4>; 257 }; 258 259 psci { 260 compatible = "arm,psci-0.2"; 261 method = "smc"; 262 }; 263 264 pmufw: firmware { 265 compatible = "xlnx,zynqmp-pm"; 266 method = "smc"; 267 interrupt-parent = <&gic>; 268 interrupts = <0 35 4>; 269 }; 270 271 timer { 272 compatible = "arm,armv8-timer"; 273 interrupt-parent = <&gic>; 274 interrupts = <1 13 0xf08>, 275 <1 14 0xf08>, 276 <1 11 0xf08>, 277 <1 10 0xf08>; 278 }; 279 280 edac { 281 compatible = "arm,cortex-a53-edac"; 282 }; 283 284 fpga_full: fpga-full { 285 compatible = "fpga-region"; 286 fpga-mgr = <&pcap>; 287 #address-cells = <2>; 288 #size-cells = <2>; 289 }; 290 291 nvmem_firmware { 292 compatible = "xlnx,zynqmp-nvmem-fw"; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 296 soc_revision: soc_revision@0 { 297 reg = <0x0 0x4>; 298 }; 299 }; 300 301 pcap: pcap { 302 compatible = "xlnx,zynqmp-pcap-fpga"; 303 }; 304 305 rst: reset-controller { 306 compatible = "xlnx,zynqmp-reset"; 307 #reset-cells = <1>; 308 }; 309 310 xlnx_dp_snd_card: dp_snd_card { 311 compatible = "xlnx,dp-snd-card"; 312 status = "disabled"; 313 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; 314 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; 315 }; 316 317 xlnx_dp_snd_codec0: dp_snd_codec0 { 318 compatible = "xlnx,dp-snd-codec"; 319 status = "disabled"; 320 clock-names = "aud_clk"; 321 }; 322 323 xlnx_dp_snd_pcm0: dp_snd_pcm0 { 324 compatible = "xlnx,dp-snd-pcm"; 325 status = "disabled"; 326 dmas = <&xlnx_dpdma 4>; 327 dma-names = "tx"; 328 }; 329 330 xlnx_dp_snd_pcm1: dp_snd_pcm1 { 331 compatible = "xlnx,dp-snd-pcm"; 332 status = "disabled"; 333 dmas = <&xlnx_dpdma 5>; 334 dma-names = "tx"; 335 }; 336 337 xilinx_drm: xilinx_drm { 338 compatible = "xlnx,drm"; 339 status = "disabled"; 340 xlnx,encoder-slave = <&xlnx_dp>; 341 xlnx,connector-type = "DisplayPort"; 342 xlnx,dp-sub = <&xlnx_dp_sub>; 343 planes { 344 xlnx,pixel-format = "rgb565"; 345 plane0 { 346 dmas = <&xlnx_dpdma 3>; 347 dma-names = "dma0"; 348 }; 349 plane1 { 350 dmas = <&xlnx_dpdma 0>, 351 <&xlnx_dpdma 1>, 352 <&xlnx_dpdma 2>; 353 dma-names = "dma0", "dma1", "dma2"; 354 }; 355 }; 356 }; 357 358 amba_apu: amba_apu@0 { 359 compatible = "simple-bus"; 360 #address-cells = <2>; 361 #size-cells = <1>; 362 ranges = <0 0 0 0 0xffffffff>; 363 364 gic: interrupt-controller@f9010000 { 365 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 366 #interrupt-cells = <3>; 367 reg = <0x0 0xf9010000 0x10000>, 368 <0x0 0xf9020000 0x20000>, 369 <0x0 0xf9040000 0x20000>, 370 <0x0 0xf9060000 0x20000>; 371 interrupt-controller; 372 interrupt-parent = <&gic>; 373 interrupts = <1 9 0xf04>; 374 }; 375 }; 376 377 amba: amba { 378 compatible = "simple-bus"; 379 u-boot,dm-pre-reloc; 380 #address-cells = <2>; 381 #size-cells = <2>; 382 ranges; 383 384 can0: can@ff060000 { 385 compatible = "xlnx,zynq-can-1.0"; 386 status = "disabled"; 387 clock-names = "can_clk", "pclk"; 388 reg = <0x0 0xff060000 0x0 0x1000>; 389 interrupts = <0 23 4>; 390 interrupt-parent = <&gic>; 391 tx-fifo-depth = <0x40>; 392 rx-fifo-depth = <0x40>; 393 power-domains = <&pd_can0>; 394 }; 395 396 can1: can@ff070000 { 397 compatible = "xlnx,zynq-can-1.0"; 398 status = "disabled"; 399 clock-names = "can_clk", "pclk"; 400 reg = <0x0 0xff070000 0x0 0x1000>; 401 interrupts = <0 24 4>; 402 interrupt-parent = <&gic>; 403 tx-fifo-depth = <0x40>; 404 rx-fifo-depth = <0x40>; 405 power-domains = <&pd_can1>; 406 }; 407 408 cci: cci@fd6e0000 { 409 compatible = "arm,cci-400"; 410 reg = <0x0 0xfd6e0000 0x0 0x9000>; 411 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 412 #address-cells = <1>; 413 #size-cells = <1>; 414 415 pmu@9000 { 416 compatible = "arm,cci-400-pmu,r1"; 417 reg = <0x9000 0x5000>; 418 interrupt-parent = <&gic>; 419 interrupts = <0 123 4>, 420 <0 123 4>, 421 <0 123 4>, 422 <0 123 4>, 423 <0 123 4>; 424 }; 425 }; 426 427 /* GDMA */ 428 fpd_dma_chan1: dma@fd500000 { 429 status = "disabled"; 430 compatible = "xlnx,zynqmp-dma-1.0"; 431 reg = <0x0 0xfd500000 0x0 0x1000>; 432 interrupt-parent = <&gic>; 433 interrupts = <0 124 4>; 434 clock-names = "clk_main", "clk_apb"; 435 xlnx,bus-width = <128>; 436 #stream-id-cells = <1>; 437 iommus = <&smmu 0x14e8>; 438 power-domains = <&pd_gdma>; 439 }; 440 441 fpd_dma_chan2: dma@fd510000 { 442 status = "disabled"; 443 compatible = "xlnx,zynqmp-dma-1.0"; 444 reg = <0x0 0xfd510000 0x0 0x1000>; 445 interrupt-parent = <&gic>; 446 interrupts = <0 125 4>; 447 clock-names = "clk_main", "clk_apb"; 448 xlnx,bus-width = <128>; 449 #stream-id-cells = <1>; 450 iommus = <&smmu 0x14e9>; 451 power-domains = <&pd_gdma>; 452 }; 453 454 fpd_dma_chan3: dma@fd520000 { 455 status = "disabled"; 456 compatible = "xlnx,zynqmp-dma-1.0"; 457 reg = <0x0 0xfd520000 0x0 0x1000>; 458 interrupt-parent = <&gic>; 459 interrupts = <0 126 4>; 460 clock-names = "clk_main", "clk_apb"; 461 xlnx,bus-width = <128>; 462 #stream-id-cells = <1>; 463 iommus = <&smmu 0x14ea>; 464 power-domains = <&pd_gdma>; 465 }; 466 467 fpd_dma_chan4: dma@fd530000 { 468 status = "disabled"; 469 compatible = "xlnx,zynqmp-dma-1.0"; 470 reg = <0x0 0xfd530000 0x0 0x1000>; 471 interrupt-parent = <&gic>; 472 interrupts = <0 127 4>; 473 clock-names = "clk_main", "clk_apb"; 474 xlnx,bus-width = <128>; 475 #stream-id-cells = <1>; 476 iommus = <&smmu 0x14eb>; 477 power-domains = <&pd_gdma>; 478 }; 479 480 fpd_dma_chan5: dma@fd540000 { 481 status = "disabled"; 482 compatible = "xlnx,zynqmp-dma-1.0"; 483 reg = <0x0 0xfd540000 0x0 0x1000>; 484 interrupt-parent = <&gic>; 485 interrupts = <0 128 4>; 486 clock-names = "clk_main", "clk_apb"; 487 xlnx,bus-width = <128>; 488 #stream-id-cells = <1>; 489 iommus = <&smmu 0x14ec>; 490 power-domains = <&pd_gdma>; 491 }; 492 493 fpd_dma_chan6: dma@fd550000 { 494 status = "disabled"; 495 compatible = "xlnx,zynqmp-dma-1.0"; 496 reg = <0x0 0xfd550000 0x0 0x1000>; 497 interrupt-parent = <&gic>; 498 interrupts = <0 129 4>; 499 clock-names = "clk_main", "clk_apb"; 500 xlnx,bus-width = <128>; 501 #stream-id-cells = <1>; 502 iommus = <&smmu 0x14ed>; 503 power-domains = <&pd_gdma>; 504 }; 505 506 fpd_dma_chan7: dma@fd560000 { 507 status = "disabled"; 508 compatible = "xlnx,zynqmp-dma-1.0"; 509 reg = <0x0 0xfd560000 0x0 0x1000>; 510 interrupt-parent = <&gic>; 511 interrupts = <0 130 4>; 512 clock-names = "clk_main", "clk_apb"; 513 xlnx,bus-width = <128>; 514 #stream-id-cells = <1>; 515 iommus = <&smmu 0x14ee>; 516 power-domains = <&pd_gdma>; 517 }; 518 519 fpd_dma_chan8: dma@fd570000 { 520 status = "disabled"; 521 compatible = "xlnx,zynqmp-dma-1.0"; 522 reg = <0x0 0xfd570000 0x0 0x1000>; 523 interrupt-parent = <&gic>; 524 interrupts = <0 131 4>; 525 clock-names = "clk_main", "clk_apb"; 526 xlnx,bus-width = <128>; 527 #stream-id-cells = <1>; 528 iommus = <&smmu 0x14ef>; 529 power-domains = <&pd_gdma>; 530 }; 531 532 gpu: gpu@fd4b0000 { 533 status = "disabled"; 534 compatible = "arm,mali-400", "arm,mali-utgard"; 535 reg = <0x0 0xfd4b0000 0x0 0x10000>; 536 interrupt-parent = <&gic>; 537 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 538 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 539 clock-names = "gpu", "gpu_pp0", "gpu_pp1"; 540 power-domains = <&pd_gpu>; 541 }; 542 543 /* LPDDMA default allows only secured access. inorder to enable 544 * These dma channels, Users should ensure that these dma 545 * Channels are allowed for non secure access. 546 */ 547 lpd_dma_chan1: dma@ffa80000 { 548 status = "disabled"; 549 compatible = "xlnx,zynqmp-dma-1.0"; 550 clock-names = "clk_main", "clk_apb"; 551 reg = <0x0 0xffa80000 0x0 0x1000>; 552 interrupt-parent = <&gic>; 553 interrupts = <0 77 4>; 554 xlnx,bus-width = <64>; 555 #stream-id-cells = <1>; 556 iommus = <&smmu 0x868>; 557 power-domains = <&pd_adma>; 558 }; 559 560 lpd_dma_chan2: dma@ffa90000 { 561 status = "disabled"; 562 compatible = "xlnx,zynqmp-dma-1.0"; 563 clock-names = "clk_main", "clk_apb"; 564 reg = <0x0 0xffa90000 0x0 0x1000>; 565 interrupt-parent = <&gic>; 566 interrupts = <0 78 4>; 567 xlnx,bus-width = <64>; 568 #stream-id-cells = <1>; 569 iommus = <&smmu 0x869>; 570 power-domains = <&pd_adma>; 571 }; 572 573 lpd_dma_chan3: dma@ffaa0000 { 574 status = "disabled"; 575 compatible = "xlnx,zynqmp-dma-1.0"; 576 clock-names = "clk_main", "clk_apb"; 577 reg = <0x0 0xffaa0000 0x0 0x1000>; 578 interrupt-parent = <&gic>; 579 interrupts = <0 79 4>; 580 xlnx,bus-width = <64>; 581 #stream-id-cells = <1>; 582 iommus = <&smmu 0x86a>; 583 power-domains = <&pd_adma>; 584 }; 585 586 lpd_dma_chan4: dma@ffab0000 { 587 status = "disabled"; 588 compatible = "xlnx,zynqmp-dma-1.0"; 589 clock-names = "clk_main", "clk_apb"; 590 reg = <0x0 0xffab0000 0x0 0x1000>; 591 interrupt-parent = <&gic>; 592 interrupts = <0 80 4>; 593 xlnx,bus-width = <64>; 594 #stream-id-cells = <1>; 595 iommus = <&smmu 0x86b>; 596 power-domains = <&pd_adma>; 597 }; 598 599 lpd_dma_chan5: dma@ffac0000 { 600 status = "disabled"; 601 compatible = "xlnx,zynqmp-dma-1.0"; 602 clock-names = "clk_main", "clk_apb"; 603 reg = <0x0 0xffac0000 0x0 0x1000>; 604 interrupt-parent = <&gic>; 605 interrupts = <0 81 4>; 606 xlnx,bus-width = <64>; 607 #stream-id-cells = <1>; 608 iommus = <&smmu 0x86c>; 609 power-domains = <&pd_adma>; 610 }; 611 612 lpd_dma_chan6: dma@ffad0000 { 613 status = "disabled"; 614 compatible = "xlnx,zynqmp-dma-1.0"; 615 clock-names = "clk_main", "clk_apb"; 616 reg = <0x0 0xffad0000 0x0 0x1000>; 617 interrupt-parent = <&gic>; 618 interrupts = <0 82 4>; 619 xlnx,bus-width = <64>; 620 #stream-id-cells = <1>; 621 iommus = <&smmu 0x86d>; 622 power-domains = <&pd_adma>; 623 }; 624 625 lpd_dma_chan7: dma@ffae0000 { 626 status = "disabled"; 627 compatible = "xlnx,zynqmp-dma-1.0"; 628 clock-names = "clk_main", "clk_apb"; 629 reg = <0x0 0xffae0000 0x0 0x1000>; 630 interrupt-parent = <&gic>; 631 interrupts = <0 83 4>; 632 xlnx,bus-width = <64>; 633 #stream-id-cells = <1>; 634 iommus = <&smmu 0x86e>; 635 power-domains = <&pd_adma>; 636 }; 637 638 lpd_dma_chan8: dma@ffaf0000 { 639 status = "disabled"; 640 compatible = "xlnx,zynqmp-dma-1.0"; 641 clock-names = "clk_main", "clk_apb"; 642 reg = <0x0 0xffaf0000 0x0 0x1000>; 643 interrupt-parent = <&gic>; 644 interrupts = <0 84 4>; 645 xlnx,bus-width = <64>; 646 #stream-id-cells = <1>; 647 iommus = <&smmu 0x86f>; 648 power-domains = <&pd_adma>; 649 }; 650 651 mc: memory-controller@fd070000 { 652 compatible = "xlnx,zynqmp-ddrc-2.40a"; 653 reg = <0x0 0xfd070000 0x0 0x30000>; 654 interrupt-parent = <&gic>; 655 interrupts = <0 112 4>; 656 }; 657 658 nand0: nand@ff100000 { 659 compatible = "arasan,nfc-v3p10"; 660 status = "disabled"; 661 reg = <0x0 0xff100000 0x0 0x1000>; 662 clock-names = "clk_sys", "clk_flash"; 663 interrupt-parent = <&gic>; 664 interrupts = <0 14 4>; 665 #address-cells = <2>; 666 #size-cells = <1>; 667 #stream-id-cells = <1>; 668 iommus = <&smmu 0x872>; 669 power-domains = <&pd_nand>; 670 }; 671 672 gem0: ethernet@ff0b0000 { 673 compatible = "cdns,zynqmp-gem"; 674 status = "disabled"; 675 interrupt-parent = <&gic>; 676 interrupts = <0 57 4>, <0 57 4>; 677 reg = <0x0 0xff0b0000 0x0 0x1000>; 678 clock-names = "pclk", "hclk", "tx_clk"; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 #stream-id-cells = <1>; 682 iommus = <&smmu 0x874>; 683 power-domains = <&pd_eth0>; 684 }; 685 686 gem1: ethernet@ff0c0000 { 687 compatible = "cdns,zynqmp-gem"; 688 status = "disabled"; 689 interrupt-parent = <&gic>; 690 interrupts = <0 59 4>, <0 59 4>; 691 reg = <0x0 0xff0c0000 0x0 0x1000>; 692 clock-names = "pclk", "hclk", "tx_clk"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 #stream-id-cells = <1>; 696 iommus = <&smmu 0x875>; 697 power-domains = <&pd_eth1>; 698 }; 699 700 gem2: ethernet@ff0d0000 { 701 compatible = "cdns,zynqmp-gem"; 702 status = "disabled"; 703 interrupt-parent = <&gic>; 704 interrupts = <0 61 4>, <0 61 4>; 705 reg = <0x0 0xff0d0000 0x0 0x1000>; 706 clock-names = "pclk", "hclk", "tx_clk"; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 #stream-id-cells = <1>; 710 iommus = <&smmu 0x876>; 711 power-domains = <&pd_eth2>; 712 }; 713 714 gem3: ethernet@ff0e0000 { 715 compatible = "cdns,zynqmp-gem"; 716 status = "disabled"; 717 interrupt-parent = <&gic>; 718 interrupts = <0 63 4>, <0 63 4>; 719 reg = <0x0 0xff0e0000 0x0 0x1000>; 720 clock-names = "pclk", "hclk", "tx_clk"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 #stream-id-cells = <1>; 724 iommus = <&smmu 0x877>; 725 power-domains = <&pd_eth3>; 726 }; 727 728 gpio: gpio@ff0a0000 { 729 compatible = "xlnx,zynqmp-gpio-1.0"; 730 status = "disabled"; 731 #gpio-cells = <0x2>; 732 interrupt-parent = <&gic>; 733 interrupts = <0 16 4>; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 reg = <0x0 0xff0a0000 0x0 0x1000>; 737 gpio-controller; 738 power-domains = <&pd_gpio>; 739 }; 740 741 i2c0: i2c@ff020000 { 742 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 743 status = "disabled"; 744 interrupt-parent = <&gic>; 745 interrupts = <0 17 4>; 746 reg = <0x0 0xff020000 0x0 0x1000>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 power-domains = <&pd_i2c0>; 750 }; 751 752 i2c1: i2c@ff030000 { 753 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 754 status = "disabled"; 755 interrupt-parent = <&gic>; 756 interrupts = <0 18 4>; 757 reg = <0x0 0xff030000 0x0 0x1000>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 power-domains = <&pd_i2c1>; 761 }; 762 763 ocm: memory-controller@ff960000 { 764 compatible = "xlnx,zynqmp-ocmc-1.0"; 765 reg = <0x0 0xff960000 0x0 0x1000>; 766 interrupt-parent = <&gic>; 767 interrupts = <0 10 4>; 768 }; 769 770 pcie: pcie@fd0e0000 { 771 compatible = "xlnx,nwl-pcie-2.11"; 772 status = "disabled"; 773 #address-cells = <3>; 774 #size-cells = <2>; 775 #interrupt-cells = <1>; 776 msi-controller; 777 device_type = "pci"; 778 interrupt-parent = <&gic>; 779 interrupts = <0 118 4>, 780 <0 117 4>, 781 <0 116 4>, 782 <0 115 4>, /* MSI_1 [63...32] */ 783 <0 114 4>; /* MSI_0 [31...0] */ 784 interrupt-names = "misc","dummy","intx", "msi1", "msi0"; 785 msi-parent = <&pcie>; 786 reg = <0x0 0xfd0e0000 0x0 0x1000>, 787 <0x0 0xfd480000 0x0 0x1000>, 788 <0x80 0x00000000 0x0 0x1000000>; 789 reg-names = "breg", "pcireg", "cfg"; 790 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 791 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 792 bus-range = <0x00 0xff>; 793 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 794 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 795 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 796 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 797 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 798 power-domains = <&pd_pcie>; 799 pcie_intc: legacy-interrupt-controller { 800 interrupt-controller; 801 #address-cells = <0>; 802 #interrupt-cells = <1>; 803 }; 804 }; 805 806 qspi: spi@ff0f0000 { 807 u-boot,dm-pre-reloc; 808 compatible = "xlnx,zynqmp-qspi-1.0"; 809 status = "disabled"; 810 clock-names = "ref_clk", "pclk"; 811 interrupts = <0 15 4>; 812 interrupt-parent = <&gic>; 813 num-cs = <1>; 814 reg = <0x0 0xff0f0000 0x0 0x1000>, 815 <0x0 0xc0000000 0x0 0x8000000>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 #stream-id-cells = <1>; 819 iommus = <&smmu 0x873>; 820 power-domains = <&pd_qspi>; 821 }; 822 823 rtc: rtc@ffa60000 { 824 compatible = "xlnx,zynqmp-rtc"; 825 status = "disabled"; 826 reg = <0x0 0xffa60000 0x0 0x100>; 827 interrupt-parent = <&gic>; 828 interrupts = <0 26 4>, <0 27 4>; 829 interrupt-names = "alarm", "sec"; 830 calibration = <0x8000>; 831 }; 832 833 serdes: zynqmp_phy@fd400000 { 834 compatible = "xlnx,zynqmp-psgtr"; 835 status = "disabled"; 836 reg = <0x0 0xfd400000 0x0 0x40000>, 837 <0x0 0xfd3d0000 0x0 0x1000>, 838 <0x0 0xff5e0000 0x0 0x1000>; 839 reg-names = "serdes", "siou", "lpd"; 840 nvmem-cells = <&soc_revision>; 841 nvmem-cell-names = "soc_revision"; 842 resets = <&rst 16>, <&rst 59>, <&rst 60>, 843 <&rst 61>, <&rst 62>, <&rst 63>, 844 <&rst 64>, <&rst 3>, <&rst 29>, 845 <&rst 30>, <&rst 31>, <&rst 32>; 846 reset-names = "sata_rst", "usb0_crst", "usb1_crst", 847 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", 848 "usb1_apbrst", "dp_rst", "gem0_rst", 849 "gem1_rst", "gem2_rst", "gem3_rst"; 850 lane0: lane0 { 851 #phy-cells = <4>; 852 }; 853 lane1: lane1 { 854 #phy-cells = <4>; 855 }; 856 lane2: lane2 { 857 #phy-cells = <4>; 858 }; 859 lane3: lane3 { 860 #phy-cells = <4>; 861 }; 862 }; 863 864 sata: ahci@fd0c0000 { 865 compatible = "ceva,ahci-1v84"; 866 status = "disabled"; 867 reg = <0x0 0xfd0c0000 0x0 0x2000>; 868 interrupt-parent = <&gic>; 869 interrupts = <0 133 4>; 870 power-domains = <&pd_sata>; 871 #stream-id-cells = <4>; 872 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 873 <&smmu 0x4c2>, <&smmu 0x4c3>; 874 /* dma-coherent; */ 875 }; 876 877 sdhci0: sdhci@ff160000 { 878 u-boot,dm-pre-reloc; 879 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 880 status = "disabled"; 881 interrupt-parent = <&gic>; 882 interrupts = <0 48 4>; 883 reg = <0x0 0xff160000 0x0 0x1000>; 884 clock-names = "clk_xin", "clk_ahb"; 885 xlnx,device_id = <0>; 886 #stream-id-cells = <1>; 887 iommus = <&smmu 0x870>; 888 power-domains = <&pd_sd0>; 889 nvmem-cells = <&soc_revision>; 890 nvmem-cell-names = "soc_revision"; 891 }; 892 893 sdhci1: sdhci@ff170000 { 894 u-boot,dm-pre-reloc; 895 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 896 status = "disabled"; 897 interrupt-parent = <&gic>; 898 interrupts = <0 49 4>; 899 reg = <0x0 0xff170000 0x0 0x1000>; 900 clock-names = "clk_xin", "clk_ahb"; 901 xlnx,device_id = <1>; 902 #stream-id-cells = <1>; 903 iommus = <&smmu 0x871>; 904 power-domains = <&pd_sd1>; 905 nvmem-cells = <&soc_revision>; 906 nvmem-cell-names = "soc_revision"; 907 }; 908 909 pinctrl0: pinctrl@ff180000 { 910 compatible = "xlnx,pinctrl-zynqmp"; 911 status = "disabled"; 912 reg = <0x0 0xff180000 0x0 0x1000>; 913 }; 914 915 smmu: smmu@fd800000 { 916 compatible = "arm,mmu-500"; 917 reg = <0x0 0xfd800000 0x0 0x20000>; 918 #iommu-cells = <1>; 919 status = "disabled"; 920 #global-interrupts = <1>; 921 interrupt-parent = <&gic>; 922 interrupts = <0 155 4>, 923 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 924 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 925 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 926 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 927 }; 928 929 spi0: spi@ff040000 { 930 compatible = "cdns,spi-r1p6"; 931 status = "disabled"; 932 interrupt-parent = <&gic>; 933 interrupts = <0 19 4>; 934 reg = <0x0 0xff040000 0x0 0x1000>; 935 clock-names = "ref_clk", "pclk"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 power-domains = <&pd_spi0>; 939 }; 940 941 spi1: spi@ff050000 { 942 compatible = "cdns,spi-r1p6"; 943 status = "disabled"; 944 interrupt-parent = <&gic>; 945 interrupts = <0 20 4>; 946 reg = <0x0 0xff050000 0x0 0x1000>; 947 clock-names = "ref_clk", "pclk"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 power-domains = <&pd_spi1>; 951 }; 952 953 ttc0: timer@ff110000 { 954 compatible = "cdns,ttc"; 955 status = "disabled"; 956 interrupt-parent = <&gic>; 957 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 958 reg = <0x0 0xff110000 0x0 0x1000>; 959 timer-width = <32>; 960 power-domains = <&pd_ttc0>; 961 }; 962 963 ttc1: timer@ff120000 { 964 compatible = "cdns,ttc"; 965 status = "disabled"; 966 interrupt-parent = <&gic>; 967 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 968 reg = <0x0 0xff120000 0x0 0x1000>; 969 timer-width = <32>; 970 power-domains = <&pd_ttc1>; 971 }; 972 973 ttc2: timer@ff130000 { 974 compatible = "cdns,ttc"; 975 status = "disabled"; 976 interrupt-parent = <&gic>; 977 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 978 reg = <0x0 0xff130000 0x0 0x1000>; 979 timer-width = <32>; 980 power-domains = <&pd_ttc2>; 981 }; 982 983 ttc3: timer@ff140000 { 984 compatible = "cdns,ttc"; 985 status = "disabled"; 986 interrupt-parent = <&gic>; 987 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 988 reg = <0x0 0xff140000 0x0 0x1000>; 989 timer-width = <32>; 990 power-domains = <&pd_ttc3>; 991 }; 992 993 uart0: serial@ff000000 { 994 u-boot,dm-pre-reloc; 995 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 996 status = "disabled"; 997 interrupt-parent = <&gic>; 998 interrupts = <0 21 4>; 999 reg = <0x0 0xff000000 0x0 0x1000>; 1000 clock-names = "uart_clk", "pclk"; 1001 power-domains = <&pd_uart0>; 1002 }; 1003 1004 uart1: serial@ff010000 { 1005 u-boot,dm-pre-reloc; 1006 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 1007 status = "disabled"; 1008 interrupt-parent = <&gic>; 1009 interrupts = <0 22 4>; 1010 reg = <0x0 0xff010000 0x0 0x1000>; 1011 clock-names = "uart_clk", "pclk"; 1012 power-domains = <&pd_uart1>; 1013 }; 1014 1015 usb0: usb0@ff9d0000 { 1016 #address-cells = <2>; 1017 #size-cells = <2>; 1018 status = "disabled"; 1019 compatible = "xlnx,zynqmp-dwc3"; 1020 reg = <0x0 0xff9d0000 0x0 0x100>; 1021 clock-names = "bus_clk", "ref_clk"; 1022 power-domains = <&pd_usb0>; 1023 ranges; 1024 nvmem-cells = <&soc_revision>; 1025 nvmem-cell-names = "soc_revision"; 1026 1027 dwc3_0: dwc3@fe200000 { 1028 compatible = "snps,dwc3"; 1029 status = "disabled"; 1030 reg = <0x0 0xfe200000 0x0 0x40000>; 1031 interrupt-parent = <&gic>; 1032 interrupts = <0 65 4>, <0 69 4>; 1033 #stream-id-cells = <1>; 1034 iommus = <&smmu 0x860>; 1035 snps,quirk-frame-length-adjustment = <0x20>; 1036 snps,refclk_fladj; 1037 /* dma-coherent; */ 1038 }; 1039 }; 1040 1041 usb1: usb1@ff9e0000 { 1042 #address-cells = <2>; 1043 #size-cells = <2>; 1044 status = "disabled"; 1045 compatible = "xlnx,zynqmp-dwc3"; 1046 reg = <0x0 0xff9e0000 0x0 0x100>; 1047 clock-names = "bus_clk", "ref_clk"; 1048 power-domains = <&pd_usb1>; 1049 ranges; 1050 nvmem-cells = <&soc_revision>; 1051 nvmem-cell-names = "soc_revision"; 1052 1053 dwc3_1: dwc3@fe300000 { 1054 compatible = "snps,dwc3"; 1055 status = "disabled"; 1056 reg = <0x0 0xfe300000 0x0 0x40000>; 1057 interrupt-parent = <&gic>; 1058 interrupts = <0 70 4>, <0 74 4>; 1059 #stream-id-cells = <1>; 1060 iommus = <&smmu 0x861>; 1061 snps,quirk-frame-length-adjustment = <0x20>; 1062 snps,refclk_fladj; 1063 /* dma-coherent; */ 1064 }; 1065 }; 1066 1067 watchdog0: watchdog@fd4d0000 { 1068 compatible = "cdns,wdt-r1p2"; 1069 status = "disabled"; 1070 interrupt-parent = <&gic>; 1071 interrupts = <0 113 1>; 1072 reg = <0x0 0xfd4d0000 0x0 0x1000>; 1073 timeout-sec = <10>; 1074 }; 1075 1076 xilinx_ams: ams@ffa50000 { 1077 compatible = "xlnx,zynqmp-ams"; 1078 status = "disabled"; 1079 interrupt-parent = <&gic>; 1080 interrupts = <0 56 4>; 1081 interrupt-names = "ams-irq"; 1082 reg = <0x0 0xffa50000 0x0 0x800>; 1083 reg-names = "ams-base"; 1084 #address-cells = <2>; 1085 #size-cells = <2>; 1086 #io-channel-cells = <1>; 1087 ranges; 1088 1089 ams_ps: ams_ps@ffa50800 { 1090 compatible = "xlnx,zynqmp-ams-ps"; 1091 status = "disabled"; 1092 reg = <0x0 0xffa50800 0x0 0x400>; 1093 }; 1094 1095 ams_pl: ams_pl@ffa50c00 { 1096 compatible = "xlnx,zynqmp-ams-pl"; 1097 status = "disabled"; 1098 reg = <0x0 0xffa50c00 0x0 0x400>; 1099 }; 1100 }; 1101 1102 xlnx_dp: dp@fd4a0000 { 1103 compatible = "xlnx,v-dp"; 1104 status = "disabled"; 1105 reg = <0x0 0xfd4a0000 0x0 0x1000>; 1106 interrupts = <0 119 4>; 1107 interrupt-parent = <&gic>; 1108 clock-names = "aclk", "aud_clk"; 1109 power-domains = <&pd_dp>; 1110 xlnx,dp-version = "v1.2"; 1111 xlnx,max-lanes = <2>; 1112 xlnx,max-link-rate = <540000>; 1113 xlnx,max-bpc = <16>; 1114 xlnx,enable-ycrcb; 1115 xlnx,colormetry = "rgb"; 1116 xlnx,bpc = <8>; 1117 xlnx,audio-chan = <2>; 1118 xlnx,dp-sub = <&xlnx_dp_sub>; 1119 xlnx,max-pclock-frequency = <300000>; 1120 }; 1121 1122 xlnx_dp_sub: dp_sub@fd4aa000 { 1123 compatible = "xlnx,dp-sub"; 1124 status = "disabled"; 1125 reg = <0x0 0xfd4aa000 0x0 0x1000>, 1126 <0x0 0xfd4ab000 0x0 0x1000>, 1127 <0x0 0xfd4ac000 0x0 0x1000>; 1128 reg-names = "blend", "av_buf", "aud"; 1129 xlnx,output-fmt = "rgb"; 1130 xlnx,vid-fmt = "yuyv"; 1131 xlnx,gfx-fmt = "rgb565"; 1132 power-domains = <&pd_dp>; 1133 }; 1134 1135 xlnx_dpdma: dma@fd4c0000 { 1136 compatible = "xlnx,dpdma"; 1137 status = "disabled"; 1138 reg = <0x0 0xfd4c0000 0x0 0x1000>; 1139 interrupts = <0 122 4>; 1140 interrupt-parent = <&gic>; 1141 clock-names = "axi_clk"; 1142 power-domains = <&pd_dp>; 1143 dma-channels = <6>; 1144 #dma-cells = <1>; 1145 dma-video0channel { 1146 compatible = "xlnx,video0"; 1147 }; 1148 dma-video1channel { 1149 compatible = "xlnx,video1"; 1150 }; 1151 dma-video2channel { 1152 compatible = "xlnx,video2"; 1153 }; 1154 dma-graphicschannel { 1155 compatible = "xlnx,graphics"; 1156 }; 1157 dma-audio0channel { 1158 compatible = "xlnx,audio0"; 1159 }; 1160 dma-audio1channel { 1161 compatible = "xlnx,audio1"; 1162 }; 1163 }; 1164 }; 1165}; 1166